Remember to clear the shadow kill flag at the same time as clearing the real
kill flag.

This could cause duplicate kill flags when the same register was used twice in a
continuous sequence of STRs.

Remember to clear the shadow kill flag at the same time as clearing the real
kill flag.

This could cause duplicate kill flags when the same register was used twice in a
continuous sequence of STRs.

There is no small test case. <rdar://problem/8218046>

llvm-svn: 112534

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When merging Thumb2 loads/stores, do not give up when the offset is one of
the special values that for ARM would be used with IB or DA modes. Fall
through and consider materializing a new base addre

When merging Thumb2 loads/stores, do not give up when the offset is one of
the special values that for ARM would be used with IB or DA modes. Fall
through and consider materializing a new base address is it would be
profitable.

llvm-svn: 112329

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Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON t

Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.

Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.

llvm-svn: 112322

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Unsigned value cannot be < 0.

llvm-svn: 112300

Reapply r110396, with fixes to appease the Linux buildbot gods.

llvm-svn: 110460

Revert r110396 to fix buildbots.

llvm-svn: 110410

Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.

llvm-svn: 110396

When no memoperands are present, assume unaligned, volatile.

llvm-svn: 107114

Use pre-increment instead of post-increment when the result is not used.

llvm-svn: 106542

Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.

llvm-svn: 106481

Make sure to skip dbg_value instructions when finding an insertion point for
the combined load/store instruction. rdar://7797940

llvm-svn: 105982

be slightly more subtle about skipping dbg_value instructions; otherwise, if a
dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last

be slightly more subtle about skipping dbg_value instructions; otherwise, if a
dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.

llvm-svn: 105758

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fix copy/paste/modify think-o

llvm-svn: 105653

Another fix to prevent debug info from affecting codegen. rdar://7797940

llvm-svn: 105470

more dbg_value adjustments so debug info doesn't affect codegen

llvm-svn: 105454

fix typo

llvm-svn: 105441

Teach the ARM load-store optimizer to deal with dbg_value instructions.

llvm-svn: 105427

Clean up 80 column violations. No functional change.

llvm-svn: 105350

Add more const qualifiers for LLVM IR pointers in CodeGen.

llvm-svn: 101342

vldm/vstm can only do up to 16 double-word registers at a time.
Radar 7797856

llvm-svn: 99630

pr6652: Use LDM to restore PC to the return address on ARMv4.
Patch by John Tytgat!

llvm-svn: 99096

Remove redundant writeback flag in ARM addressing mode 5.

llvm-svn: 98648

Remove the writeback flag from ARM's address mode 4. Now that we have separate
instructions for ld/st with writeback, the flag is completely redundant.

llvm-svn: 98643

Wrap a long line and add some parens to be consistent.

llvm-svn: 98596

Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback regi

Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.

llvm-svn: 98409

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