Clean up some code for clarity.

llvm-svn: 128953

Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases.

llvm-svn: 128481

Add safety check that didn't show up in testing.

llvm-svn: 128467

Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.

llvm-svn: 128461

Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587

llvm-svn: 127683

Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.

This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a me

Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.

This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:

STR %R0, a...
STR %R0<kill>, b...

First becomes:

STR %R0, b...
STM a, %R0<kill>, ...

and then:

STM a, %R0, ...
STM b, %R0<kill>, ...

We can now remove the kill flag from the merged STM when needed. 8960050.

llvm-svn: 125591

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Move code for OffsetCompare struct closer to where it is used.

llvm-svn: 125009

Fix a few more places that should use MBB::getLastNonDebugInstr().

llvm-svn: 123408

Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnm

Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.

llvm-svn: 123044

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PR8921: LDM/POP do not support interworking prior to v5t.

llvm-svn: 122970

Missed the _RET versions of LDMIA.

llvm-svn: 119726

Add missing opcodes now that this function's used in more than one place.

llvm-svn: 119539

Revert r119109 for now. It's breaking 176.gcc.

llvm-svn: 119492

The machine instruction no longer encodes the submode as a separate operand. We
should get the submode from the load/store multiple instruction's opcode.

llvm-svn: 119461

Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm pars

Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310

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Make sure ARM multi load / store pass copies memoperands when forming ldrd / strd. pr8113.

llvm-svn: 119109

Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign sche

Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505

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One more spot where the new arm mode LDR instruction representation
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

llvm-svn: 117421

First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, am

First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409

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Grammar.

llvm-svn: 117388

Transfer implicit ops when forming load multiple and return instructions.

llvm-svn: 117151

Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 848

Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.

llvm-svn: 115047

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move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to

move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.

llvm-svn: 114016

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Calculate the number of VLDM/VSTM registers by subtracting the number of
fixed operands from the total number of operands (including the variadic ones).

llvm-svn: 113597

Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
to use AddrMode4, there was a count of the registers stored in one of the
operands. I changed that to just count the oper

Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
to use AddrMode4, there was a count of the registers stored in one of the
operands. I changed that to just count the operands but forgot to adjust for
the size of D registers. This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.

llvm-svn: 113576

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