[ARM] Do not test for CPUs, use SubtargetFeatures (Part 3). NFCI

This is a follow-up for r273544 and r273853.

The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods.
This commi

[ARM] Do not test for CPUs, use SubtargetFeatures (Part 3). NFCI

This is a follow-up for r273544 and r273853.

The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods.
This commit also marks them as obsolete.

Differential Revision: http://reviews.llvm.org/D21796

llvm-svn: 274616

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Pass DebugLoc and SDLoc by const ref.

This used to be free, copying and moving DebugLocs became expensive
after the metadata rewrite. Passing by reference eliminates a ton of
track/untrack operation

Pass DebugLoc and SDLoc by const ref.

This used to be free, copying and moving DebugLocs became expensive
after the metadata rewrite. Passing by reference eliminates a ton of
track/untrack operations. No functionality change intended.

llvm-svn: 272512

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[ARM] Transform LDMs into writeback form to save code size

If we have an LDM that uses only low registers and doesn't write to its base register:

ldm.w r0, {r1, r2, r3}

And that base register is

[ARM] Transform LDMs into writeback form to save code size

If we have an LDM that uses only low registers and doesn't write to its base register:

ldm.w r0, {r1, r2, r3}

And that base register is dead after the LDM, then we can convert it to writeback form and use a narrow encoding:

ldm.n r0!, {r1, r2, r3}

Obviously, this introduces a new register write and so can cause WAW hazards, so I've enabled it only in minsize mode. This is a code size trick that ARM Compiler 5 ("armcc") does that we don't.

llvm-svn: 272000

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livePhysRegs: Pass MBB by reference in addLive{Ins|Outs}(); NFC

The block must no be nullptr for the addLiveIns()/addLiveOuts()
function.

llvm-svn: 268340

LivePhysRegs: Automatically determine presence of pristine regs.

Remove the AddPristinesAndCSRs parameters from
addLiveIns()/addLiveOuts().

We need to respect pristine registers after prologue epil

LivePhysRegs: Automatically determine presence of pristine regs.

Remove the AddPristinesAndCSRs parameters from
addLiveIns()/addLiveOuts().

We need to respect pristine registers after prologue epilogue insertion,
Seeing that we got this wrong in at least two commits already, we should
rather pay the small price to query MachineFrameInfo for it.

There are three cases that did not set AddPristineAndCSRs to true even
after register allocation:
- ExecutionDepsFix: live-out registers are used as a hint that the
register is used soon. This is not true for pristine registers so
use the new addLiveOutsNoPristines() to maintain this behaviour.
- SystemZShortenInst: Not setting AddPristineAndCSRs to true looks like
a bug, should do the right thing automatically now.
- StackMapLivenessAnalysis: Not adding pristine registers looks like a
bug to me. Added a FIXME comment but maintain the current behaviour
as a change may need to get coordinated with GC runtimes.

llvm-svn: 268336

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Add optimization bisect opt-in calls for ARM passes

Differential Revision: http://reviews.llvm.org/D19449

llvm-svn: 267480

Add MachineFunctionProperty checks for AllVRegsAllocated for target passes

Summary:
This adds the same checks that were added in r264593 to all
target-specific passes that run after register allocat

Add MachineFunctionProperty checks for AllVRegsAllocated for target passes

Summary:
This adds the same checks that were added in r264593 to all
target-specific passes that run after register allocation.

Reviewers: qcolombet

Subscribers: jyknight, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18525

llvm-svn: 265313

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ARM: Introduce conservative load/store optimization mode

Most of the time ARM has the CCR.UNALIGN_TRP bit set to false which
means that unaligned loads/stores do not trap and even extensive testing

ARM: Introduce conservative load/store optimization mode

Most of the time ARM has the CCR.UNALIGN_TRP bit set to false which
means that unaligned loads/stores do not trap and even extensive testing
will not catch these bugs. However the multi/double variants are not
affected by this bit and will still trap. In effect a more aggressive
load/store optimization will break existing (bad) code.

These bugs do not necessarily manifest in the broken code where the
misaligned pointer is formed but often later in perfectly legal code
where it is accessed. This means recompiling system libraries (which
have no alignment bugs) with a newer compiler will break existing
applications (with alignment bugs) that worked before.

So (under protest) I implemented this safe mode which limits the
formation of multi/double operations to cases that are not affected by
user code (stack operations like spills/reloads) or cases where the
normal operations trap anyway (floating point load/stores). It is
disabled by default.

Differential Revision: http://reviews.llvm.org/D17015

llvm-svn: 262504

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CodeGen: Change MachineInstr to use MachineInstr&, NFC

Change MachineInstr API to prefer MachineInstr& over MachineInstr*
whenever the parameter is expected to be non-null. Slowly inching
toward be

CodeGen: Change MachineInstr to use MachineInstr&, NFC

Change MachineInstr API to prefer MachineInstr& over MachineInstr*
whenever the parameter is expected to be non-null. Slowly inching
toward being able to fix PR26753.

llvm-svn: 262149

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CodeGen: TII: Take MachineInstr& in predicate API, NFC

Change TargetInstrInfo API to take `MachineInstr&` instead of
`MachineInstr*` in the functions related to predicated instructions
(I'll try to

CodeGen: TII: Take MachineInstr& in predicate API, NFC

Change TargetInstrInfo API to take `MachineInstr&` instead of
`MachineInstr*` in the functions related to predicated instructions
(I'll try to come back later and get some of the rest). All of these
functions require non-null parameters already, so references are more
clear. As a bonus, this happens to factor away a host of implicit
iterator => pointer conversions.

No functionality change intended.

llvm-svn: 261605

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Extract helper function to merge MemoryOperand lists [NFC]

In the discussion on http://reviews.llvm.org/D15730, Andy pointed out we had a utility function for merging MMO lists. Since it turned we a

Extract helper function to merge MemoryOperand lists [NFC]

In the discussion on http://reviews.llvm.org/D15730, Andy pointed out we had a utility function for merging MMO lists. Since it turned we actually had two copies and there's another review in progress (http://reviews.llvm.org/D15230) which needs the same, extract it into a utility function and clean up the interfaces to make it easier to use with a MachineInstBuilder.

I introduced a pair here to track size and allocation together. I think we should probably move in the direction of the MachineOperandsRef helper class, but I'm leaving that for further work. I want to get the poison state introduced before I make major changes to the interface.

Differential Revision: http://reviews.llvm.org/D15757

llvm-svn: 256909

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[Thumb] Fix assembler error 'cannot honor width suffix pop {lr}'

Summary:
* avoid generating POP {LR} in Thumb1 epilogues
* combine MOV LR, Rx + BX LR -> BX Rx in a peephole optimization pass
* comb

[Thumb] Fix assembler error 'cannot honor width suffix pop {lr}'

Summary:
* avoid generating POP {LR} in Thumb1 epilogues
* combine MOV LR, Rx + BX LR -> BX Rx in a peephole optimization pass
* combine POP {LR} + B + BX LR -> POP {PC} on v5T+

Test cases by Ana Pazos

Differential Revision: http://reviews.llvm.org/D15707

llvm-svn: 256523

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Teach ARMLoadStoreOptimizer to ignore DBG_VALUE instructions when merging
instructions.

As noted in PR24563.
rdar://problem/23963293

llvm-svn: 256183

ARMLoadStoreOptimizer: Cleanup isMemoryOp(); NFC

llvm-svn: 253757

ARM: Remove implicit ilist iterator conversions, NFC

llvm-svn: 250759

[ARM] More care with Thumb1 writeback in ARMLoadStoreOptimizer

Differential Revision: http://reviews.llvm.org/D13240

llvm-svn: 249002

[ARM] Register ARMPreAllocLoadStoreOpt pass with LLVM pass manager.

llvm-svn: 247791

[ARM] Remove an unused reference to MachineRegisterInfo. NFC.

llvm-svn: 244334

[ARM] Register (existing) ARMLoadStoreOpt pass with LLVM pass manager.

Summary: Among other things, this allows -print-after-all/-print-before-all to dump IR around this pass.

Subscribers: aemerson

[ARM] Register (existing) ARMLoadStoreOpt pass with LLVM pass manager.

Summary: Among other things, this allows -print-after-all/-print-before-all to dump IR around this pass.

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D11373

llvm-svn: 243052

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Test commit.

llvm-svn: 243046

ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code

Re-apply of r241928 which had to be reverted because of the r241926
revert.

This commit factors out common code from MergeBas

ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code

Re-apply of r241928 which had to be reverted because of the r241926
revert.

This commit factors out common code from MergeBaseUpdateLoadStore() and
MergeBaseUpdateLSMultiple() and introduces a new function
MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a
strd/ldrd instruction into an strd/ldrd instruction with writeback where
possible.

Differential Revision: http://reviews.llvm.org/D10676

llvm-svn: 242743

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ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2

Re-apply r241926 with an additional check that r13 and r15 are not used
for LDRD/STRD. See http://llvm.org/PR24190. This also already includes
the f

ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2

Re-apply r241926 with an additional check that r13 and r15 are not used
for LDRD/STRD. See http://llvm.org/PR24190. This also already includes
the fix from r241951.

Differential Revision: http://reviews.llvm.org/D10623

llvm-svn: 242742

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Revert "ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2"

This reverts commit r241926. This caused http://llvm.org/PR24190

llvm-svn: 242735

Revert "ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code"

This reverts commit r241928. This caused http://llvm.org/PR24190

llvm-svn: 242734

Revert "ARM: Use SpecificBumpPtrAllocator to fix leak introduced in r241920"

This reverts commit r241951. It caused http://llvm.org/PR24190

llvm-svn: 242733