AMDGPU: Add support for isa version note

- Emit NT_AMD_AMDGPU_ISA
- Add assembler parsing for isa version directive
- If isa version directive does not match command line arguments, then ret

AMDGPU: Add support for isa version note

- Emit NT_AMD_AMDGPU_ISA
- Add assembler parsing for isa version directive
- If isa version directive does not match command line arguments, then return error

Differential Revision: https://reviews.llvm.org/D38748

llvm-svn: 315808

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[AMDGPU] calling conventions for AMDPAL OS type

Summary:
This commit adds comments on how the AMDPAL OS type overloads the
existing AMDGPU_ calling conventions used by Mesa, and adds a couple of
new

[AMDGPU] calling conventions for AMDPAL OS type

Summary:
This commit adds comments on how the AMDPAL OS type overloads the
existing AMDGPU_ calling conventions used by Mesa, and adds a couple of
new ones.

Reviewers: arsenm, nhaehnle, dstuttard

Subscribers: mehdi_amini, kzhuravl, wdng, yaxunl, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D37752

llvm-svn: 314502

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AMDGPU: Cleanup subtarget features

Try to avoid mutually exclusive features. Don't use
a real default GPU, and use a fake "generic". The goal
is to make it easier to see which set of features are
in

AMDGPU: Cleanup subtarget features

Try to avoid mutually exclusive features. Don't use
a real default GPU, and use a fake "generic". The goal
is to make it easier to see which set of features are
incompatible between feature strings.

Most of the test changes are due to random scheduling changes
from not having a default fullspeed model.

llvm-svn: 310258

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AMDGPU: Fix using SMRD instructions for argument loads in functions

These are not actually uniform values except in kernels.

llvm-svn: 309172

[AMDGPU][MC] Optimized IsRegIntersect function

Optimized IsRegIntersect by using MCRegAliasIterator

See Bug 33800: https://bugs.llvm.org//show_bug.cgi?id=33800

Reviewers: arsenm, artem.tamazov

Di

[AMDGPU][MC] Optimized IsRegIntersect function

Optimized IsRegIntersect by using MCRegAliasIterator

See Bug 33800: https://bugs.llvm.org//show_bug.cgi?id=33800

Reviewers: arsenm, artem.tamazov

Differential Revision: https://reviews.llvm.org/D35452

llvm-svn: 308294

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Revert "AMDGPU: Do not test for SI in getIsaVersion"

This reverts commit r307573.

This breaks downstream test.

llvm-svn: 307678

AMDGPU: Do not test for SI in getIsaVersion

SI is being tested by isa version in the first two if statements of the function.

llvm-svn: 307573

[AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is different than any of the src

See Bug 33279: https://bugs.llvm.org//show_bug.cgi?id=33279

Reviewers: artem.tamazov, vpykh

[AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is different than any of the src

See Bug 33279: https://bugs.llvm.org//show_bug.cgi?id=33279

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D34003

llvm-svn: 305915

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AMDGPU : Fix ISA Version Definitions.

Differential Revision: http://reviews.llvm.org/D28531

llvm-svn: 305137

Move Object format code to lib/BinaryFormat.

This creates a new library called BinaryFormat that has all of
the headers from llvm/Support containing structure and layout
definitions for various type

Move Object format code to lib/BinaryFormat.

This creates a new library called BinaryFormat that has all of
the headers from llvm/Support containing structure and layout
definitions for various types of binary formats like dwarf, coff,
elf, etc as well as the code for identifying a file from its
magic.

Differential Revision: https://reviews.llvm.org/D33843

llvm-svn: 304864

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Sort the remaining #include lines in include/... and lib/....

I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line

Sort the remaining #include lines in include/... and lib/....

I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line with a #include and let it re-sort things according to the precise
LLVM rules for include ordering baked into clang-format these days.

I've reverted a number of files where the results of sorting includes
isn't healthy. Either places where we have legacy code relying on
particular include ordering (where possible, I'll fix these separately)
or where we have particular formatting around #include lines that
I didn't want to disturb in this patch.

This patch is *entirely* mechanical. If you get merge conflicts or
anything, just ignore the changes in this patch and run clang-format
over your #include lines in the files.

Sorry for any noise here, but it is important to keep these things
stable. I was seeing an increasing number of patches with irrelevant
re-ordering of #include lines because clang-format was used. This patch
at least isolates that churn, makes it easy to skip when resolving
conflicts, and gets us to a clean baseline (again).

llvm-svn: 304787

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AMDGPU: Remove deprecated and unused elf definitions

Differential Revision: https://reviews.llvm.org/D33689

llvm-svn: 304737

Revert "AMDGPU: Fold CI-specific complex SMRD patterns into existing complex patterns"

This reverts commit e065977c4b5f68ab845400b256f6a3822b1325fa.

It doesn't work. S_LOAD_DWORD_IMM_ci and friends

Revert "AMDGPU: Fold CI-specific complex SMRD patterns into existing complex patterns"

This reverts commit e065977c4b5f68ab845400b256f6a3822b1325fa.

It doesn't work. S_LOAD_DWORD_IMM_ci and friends aren't selected by any of
the patterns, so it was putting 32-bit literals into the 8-bit field.

llvm-svn: 303754

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AMDGPU: Fold CI-specific complex SMRD patterns into existing complex patterns

This is just a cleanup. Also, it adds checking that ByteCount is aligned to 4.

Reviewers: arsenm, nhaehnle, tstellarAMD

AMDGPU: Fold CI-specific complex SMRD patterns into existing complex patterns

This is just a cleanup. Also, it adds checking that ByteCount is aligned to 4.

Reviewers: arsenm, nhaehnle, tstellarAMD

Subscribers: kzhuravl, wdng, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D28994

llvm-svn: 303658

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[AMDGPU] SDWA: Add assembler support for GFX9

Summary:
Added separate pseudo and real instruction for GFX9 SDWA instructions.
Currently supports only in assembler.
Depends D32493

Reviewers: vpykhti

[AMDGPU] SDWA: Add assembler support for GFX9

Summary:
Added separate pseudo and real instruction for GFX9 SDWA instructions.
Currently supports only in assembler.
Depends D32493

Reviewers: vpykhtin, artem.tamazov

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D33132

llvm-svn: 303620

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AMDGPU: Start defining a calling convention

Partially implement callee-side for arguments and return values.
byval doesn't work properly, and most likely sret or other on-stack
return values most as

AMDGPU: Start defining a calling convention

Partially implement callee-side for arguments and return values.
byval doesn't work properly, and most likely sret or other on-stack
return values most as well.

llvm-svn: 303308

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AMDGPU: Add AMDGPU_HS calling convention

Reviewers: arsenm, nhaehnle

Subscribers: mehdi_amini, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.ll

AMDGPU: Add AMDGPU_HS calling convention

Reviewers: arsenm, nhaehnle

Subscribers: mehdi_amini, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D32644

llvm-svn: 301930

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AMDGPU: Temporarily disable packed inlinable literals (v2f16, v2i16)

Differential Revision: https://reviews.llvm.org/D32361

llvm-svn: 301028

AMDGPU: Refactor argument lowering

Split into smaller functions and prepare for handling
non-entry functions.

llvm-svn: 299998

AMDGPU: Fix crash when disassembling VOP3 mac

The unused dummy src2_modifiers is missing, so it crashes
when trying to print it.

I tried to fully remove src2_modifiers, but there are some
irritatio

AMDGPU: Fix crash when disassembling VOP3 mac

The unused dummy src2_modifiers is missing, so it crashes
when trying to print it.

I tried to fully remove src2_modifiers, but there are some
irritations in the places where it is converted to mad since
it starts to require modifying use lists while iterating over
them.

llvm-svn: 299861

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[AMDGPU] Temporarily change constant address space from 4 to 2

Our final address space mapping is to let constant address space to be 4 to match nvptx.
However for now we will make it 2 to avoid unn

[AMDGPU] Temporarily change constant address space from 4 to 2

Our final address space mapping is to let constant address space to be 4 to match nvptx.
However for now we will make it 2 to avoid unnecessary work in FE/BE/devlib
about intrinsics returning constant pointers.

Differential Revision: https://reviews.llvm.org/D31770

llvm-svn: 299690

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[AMDGPU] Get address space mapping by target triple environment

As we introduced target triple environment amdgiz and amdgizcl, the address
space values are no longer enums. We have to decide the va

[AMDGPU] Get address space mapping by target triple environment

As we introduced target triple environment amdgiz and amdgizcl, the address
space values are no longer enums. We have to decide the value by target triple.

The basic idea is to use struct AMDGPUAS to represent address space values.
For address space values which are not depend on target triple, use static
const members, so that they don't occupy extra memory space and is equivalent
to a compile time constant.

Since the struct is lightweight and cheap, it can be created on the fly at
the point of usage. Or it can be added as member to a pass and created at
the beginning of the run* function.

Differential Revision: https://reviews.llvm.org/D31284

llvm-svn: 298846

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[AMDGPU][MC] Fix for Bug 30829 + LIT tests

Added code to check constant bus restrictions for VOP formats (only one SGPR value or literal-constant may be used by the instruction).
Note that the same

[AMDGPU][MC] Fix for Bug 30829 + LIT tests

Added code to check constant bus restrictions for VOP formats (only one SGPR value or literal-constant may be used by the instruction).
Note that the same checks are performed by SIInstrInfo::verifyInstruction (used by lowering code).
Added LIT tests.

llvm-svn: 296873

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[AMDGPU] Change amd_kernel_code_t's minor version to 1
- We do emit amd_kernel_code_t v1.1

Differential Revision: https://reviews.llvm.org/D30433

llvm-svn: 296489

AMDGPU: Add VOP3P instruction format

Add a few non-VOP3P but instructions related to packed.

Includes hack with dummy operands for the benefit of the assembler

llvm-svn: 296368