AMDGPU: Assume true in getVOPNIsSingle helpers (#98516)

If we have something we don't know what it is, we should conservatively
avoid printing an additional suffix. For isCodeGenOnly
pseudoinstruc

AMDGPU: Assume true in getVOPNIsSingle helpers (#98516)

If we have something we don't know what it is, we should conservatively
avoid printing an additional suffix. For isCodeGenOnly
pseudoinstructions,
no encoded instruction is added to the tables this is queried, and the
null
case would assume true.

This happens to fix the case I ran into, but this isn't a wholistic fix.
These really should be encoded directly in the TSFlags of the
MCInstrDesc,
which would allow encoding pseudos to work correctly.

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[AMDGPU] Fix negative immediate offset for unbuffered smem loads (#89165)

For unbuffered smem loads, it is illegal for the immediate offset to be
negative if the resulting IOFFSET + (SGPR[Offset] o

[AMDGPU] Fix negative immediate offset for unbuffered smem loads (#89165)

For unbuffered smem loads, it is illegal for the immediate offset to be
negative if the resulting IOFFSET + (SGPR[Offset] or M0 or zero) is
negative.

New PR of https://github.com/llvm/llvm-project/pull/79553.

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AMDGPU: Support local atomicrmw fmin/fmax for float/double (#95590)

This has always been supported. Somehow, we ended up with 2
copies of clang builtins for this case, and the newer one
erroneously

AMDGPU: Support local atomicrmw fmin/fmax for float/double (#95590)

This has always been supported. Somehow, we ended up with 2
copies of clang builtins for this case, and the newer one
erroneously requires gfx8-insts.

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[AMDGPU] Exclude certain opcodes from being marked as single use (#91802)

The s_singleuse_vdst instruction is used to mark regions of instructions
that produce values that have only one use.
Certa

[AMDGPU] Exclude certain opcodes from being marked as single use (#91802)

The s_singleuse_vdst instruction is used to mark regions of instructions
that produce values that have only one use.
Certain instructions take more than one cycle to execute, resulting in
regions being incorrectly marked.
This patch excludes these multi-cycle instructions from being marked as
either producing single use values or consuming single use values
or both depending on the instruction.

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MCExpr-ify amd_kernel_code_t (#91587)

Redefines the amd_kernel_code_t struct with MCExprs for members that would be
derived from SIProgramInfo MCExpr members.

MCExpr-ify SIProgramInfo (#88257)

Convert members in SIProgramInfo affected by variables provided by AMDGPUResourceUsageAnalysis into MCExprs.

[AMDGPU][MC] Disable sendmsg SYSMSG_OP_HOST_TRAP_ACK on gfx9+ (#90203)

This is no longer supported as of gfx9. Fixes #52903

This commit also includes some refactoring of sendmsg operand parsing:

[AMDGPU][MC] Disable sendmsg SYSMSG_OP_HOST_TRAP_ACK on gfx9+ (#90203)

This is no longer supported as of gfx9. Fixes #52903

This commit also includes some refactoring of sendmsg operand parsing:
- Use CustomOperand for sendmsg operations, this allows them to be
conditionally available based on a STI check (and automatically in
sync with SIDefines.h).
- Move CustomOperand table lookups from AMDGPUBaseInfo to
AMDGPUAsmUtils. This cleans up an awkward interface where
AMDGPUAsmUtils defined a table/size as globals that AMDGPUBaseInfo
had to loop over.
- Clean up a few of the operand lookup functions while moving them.

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[AMDGPU] Add a missing COV6 case to getAMDHSACodeObjectVersion() (#87492)

[AMDGPU][MC] Allow VOP3C dpp src1 to be imm or SGPR (#87418)

Allows src1 of VOP3 encoded VOPC to be an SGPR or inline immediate on
GFX1150Plus

The w32 and w64 _e64_dpp assembler only real instru

[AMDGPU][MC] Allow VOP3C dpp src1 to be imm or SGPR (#87418)

Allows src1 of VOP3 encoded VOPC to be an SGPR or inline immediate on
GFX1150Plus

The w32 and w64 _e64_dpp assembler only real instructions were unused,
and erroneously constructed in a way that bugged parsing of the new
instructions. They are removed.

This patch is a follow up to PR
https://github.com/llvm/llvm-project/pull/87382

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Reland [AMDGPU] MCExpr-ify MC layer kernel descriptor (#86494)

Kernel descriptor attributes, with their respective emit and asm parse functionality, converted to MCExpr.

Relands #80855 with fixes

[AMDGPU][NFC] Rename Feature GFX11FullVGPRs to 1_5xVGPRs (#86468)

[AMDGPU] Extend zero initialization of return values for TFE (#85759)

buffer_load instructions that use TFE also need to zero initialize
return values similar to how the image instructions currentl

[AMDGPU] Extend zero initialization of return values for TFE (#85759)

buffer_load instructions that use TFE also need to zero initialize
return values similar to how the image instructions currently work. Add
support for this with standard zero init of all results + zero init of
just TFE flag when enable-prt-strict-null subtarget feature is disabled.

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Revert "[AMDGPU] MCExpr-ify MC layer kernel descriptor" (#86151)

Reverts llvm/llvm-project#80855

[AMDGPU] MCExpr-ify MC layer kernel descriptor (#80855)

Kernel descriptor attributes, with their respective emit and asm parse functionality, converted to MCExpr.

Reapply "[AMDGPU] Add pal metadata 3.0 support to callable pal funcs (#67104)"

This reverts commit 7d508eb5d38f4bbbab4230a666d9e742e271af61.

[AMDGPU] Adding the amdgpu_num_work_groups function attribute (#79035)

A new function attribute named amdgpu_num_work_groups is added. This
attribute, which consists of three integers, allows progr

[AMDGPU] Adding the amdgpu_num_work_groups function attribute (#79035)

A new function attribute named amdgpu_num_work_groups is added. This
attribute, which consists of three integers, allows programmers to let
the compiler know the number of workgroups to be launched in each of the
three dimensions and do optimizations based on that information.

---------

Co-authored-by: Jun Wang <jun.wang7@amd.com>

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[AMDGPU] Replace `isInlinableLiteral16` with specific version (#84402)

The current implementation of `isInlinableLiteral16` assumes, a 16-bit
inlinable
literal is either an `i16` or a `fp16`. This

[AMDGPU] Replace `isInlinableLiteral16` with specific version (#84402)

The current implementation of `isInlinableLiteral16` assumes, a 16-bit
inlinable
literal is either an `i16` or a `fp16`. This is not always true because
of
`bf16`. However, we can't tell `fp16` and `bf16` apart by just looking
at the
value. This patch splits `isInlinableLiteral16` into three versions,
`i16`,
`fp16`, `bf16` respectively, and call the corresponding version.

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[AMDGPU] Rename getNumVGPRBlocks. NFC (#84161)

Rename getNumVGPRBlocks to getEncodedNumVGPRBlocks, to clarify that it's
using the encoding granule. This is used to program the hardware. In
practic

[AMDGPU] Rename getNumVGPRBlocks. NFC (#84161)

Rename getNumVGPRBlocks to getEncodedNumVGPRBlocks, to clarify that it's
using the encoding granule. This is used to program the hardware. In
practice, the hardware will use the alloc granule instead, so this patch
also adds a new helper, getAllocatedNumVGPRBlocks, which can be useful
when driving heuristics.

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[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)

The previous name 'amdgpu_code_object_version', was misleading since
this is really a property of the HSA OS. The new spelling

[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)

The previous name 'amdgpu_code_object_version', was misleading since
this is really a property of the HSA OS. The new spelling also matches
the asm directive I added in bc82cfb.

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Revert "[AMDGPU] Replace `isInlinableLiteral16` with specific version (#81345)"

This reverts commit 530f0e64ec11327879c44f2fd55c7c28efdbaa2d because it breaks
downstream.

[AMDGPU] Replace `isInlinableLiteral16` with specific version (#81345)

[AMDGPU][AsmParser] Support structured HWREG operands. (#82805)

Symbolic values are to be supported separately.

[AMDGPU] Prefer lower total register usage in regions with spilling

Change-Id: Ia5c434b0945bdcbc357c5e06c3164118fc91df25

[AMDGPU][NFC] Have helpers to deal with encoding fields. (#82772)

These are hoped to provide more convenient and less error prone
facilities to encode and decode fields than manually defined consta

[AMDGPU][NFC] Have helpers to deal with encoding fields. (#82772)

These are hoped to provide more convenient and less error prone
facilities to encode and decode fields than manually defined constants
and functions.

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[AMDGPU] Use `bf16` instead of `i16` for bfloat (#80908)

Currently we generally use `i16` to represent `bf16` in those tablegen
files. This patch is trying to use `bf16` directly.

Fix #79369.