[AMDGPU][Disassembler] Fix a spurious error message in an instruction comment.

The patch prevents pollution of instruction comments with error messages
generated during unsuccessful decoding attempt

[AMDGPU][Disassembler] Fix a spurious error message in an instruction comment.

The patch prevents pollution of instruction comments with error messages
generated during unsuccessful decoding attempts.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D149049

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[AMDGPU][MC][GFX11] Add Partial NSA format for image sample instructions

Image sample instructions that need more than 5 VGPRs for VAddr can use
partial NSA for NSA encoding format. VGPRs that can n

[AMDGPU][MC][GFX11] Add Partial NSA format for image sample instructions

Image sample instructions that need more than 5 VGPRs for VAddr can use
partial NSA for NSA encoding format. VGPRs that can not fit into the
encoding are sequential after the last one.
This patch adds assembly and disassembly parts.

Differential Revision: https://reviews.llvm.org/D144033

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Simplify with hasFeature. NFC

Use llvm::bit_cast (NFC)

AMDGPU: Use module flag to get code object version at IR level folow-up

Summary:
This is part of the leftover work for https://reviews.llvm.org/D143138.
In this work, we pass code object version a

AMDGPU: Use module flag to get code object version at IR level folow-up

Summary:
This is part of the leftover work for https://reviews.llvm.org/D143138.
In this work, we pass code object version as an argument to initialize target ID
and use it for targetID dump.

Reviewers: arsenm

Differential Revision
https://reviews.llvm.org/D143293

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AMDGPU/MC: Fix decoders for VSrc_v2b32 and VSrc_v2f32 RegisterOperands

Decoder should make 32 bit value when decoding immediates, not 64 bit.

Differential Revision: https://reviews.llvm.org/D143574

AMDGPU/MC: Fix indentation and remove unused macro after D142636

AMDGPU/MC: Refactor decoders. Rework decoders for float immediates

decodeFPImmed creates immediate operand using register operand width,
but size of created immediate should correspond to OperandTyp

AMDGPU/MC: Refactor decoders. Rework decoders for float immediates

decodeFPImmed creates immediate operand using register operand width,
but size of created immediate should correspond to OperandType for
RegisterOperand.
e.g. OPW128 could be used for RegisterOperands that use v2f64 v4f32
and v8f16. Each RegisterOperands would have different OperandType and
require that immediate is decoded using 64, 32 and 16 bit immediate
respectively.
decodeOperand_<RegClass> only provides width for register decoding,
introduce decodeOperand_<RegClass>_Imm<ImmWidth> that also provides
width for immediate decoding.
Refactor RegisterOperands:
- decoders get _Imm<ImmWidth> suffix in some cases
- removed unused RegisterOperands defined via multiclass
- use different RegisterOperand in a few places, new RegisterOperand's
decoder corresponds to the number of bits used for operand's encoding
Refactor decoder functions:
- add asserts for the size of encoding that will be decoded
- regroup them according to the method of decoding
decodeOperand_<RegClass> (register only, no immediate) decoders can now
create immediate of consistent size, use it for better diagnostic of
'invalid immediate'.

Differential Revision: https://reviews.llvm.org/D142636

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[MC] Make more use of MCInstrDesc::operands. NFC.

Change MCInstrDesc::operands to return an ArrayRef so we can easily use
it everywhere instead of the (IMHO ugly) opInfo_begin and opInfo_end.
A futu

[MC] Make more use of MCInstrDesc::operands. NFC.

Change MCInstrDesc::operands to return an ArrayRef so we can easily use
it everywhere instead of the (IMHO ugly) opInfo_begin and opInfo_end.
A future patch will remove opInfo_begin and opInfo_end.

Also use it instead of raw access to the OpInfo pointer. A future patch
will remove this pointer.

Differential Revision: https://reviews.llvm.org/D142213

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Use llvm::popcount instead of llvm::countPopulation(NFC)

[MC] llvm::Optional => std::optional

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716

[Target] Use std::nullopt instead of None (NFC)

This patch mechanically replaces None with std::nullopt where the
compiler would warn if None were deprecated. The intent is to reduce
the amount of

[Target] Use std::nullopt instead of None (NFC)

This patch mechanically replaces None with std::nullopt where the
compiler would warn if None were deprecated. The intent is to reduce
the amount of manual work required in migrating from Optional to
std::optional.

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716

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[AMDGPU] Add support for new LLVM vector types

Add VReg, AReg and SReg on AMDGPU for bit widths: 288, 320, 352 and 384.

Differential Revision: https://reviews.llvm.org/D138205

[AMDGPU][MC][MI100+] Enable VOP3 variants of dot2c/dot4c/dot8c opcodes

Differential Revision: https://reviews.llvm.org/D138494

[AMDGPU] Make aperture registers 64 bit

Makes the SRC_(SHARED|PRIVATE)_(BASE|LIMIT) registers 64 bit instead of 32.
They're still usable as 32 bit operands by using the _LO suffix.

Preparation for

[AMDGPU] Make aperture registers 64 bit

Makes the SRC_(SHARED|PRIVATE)_(BASE|LIMIT) registers 64 bit instead of 32.
They're still usable as 32 bit operands by using the _LO suffix.

Preparation for D137542

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D137767

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[AMDGPU][MC] Support TFE modifiers in MUBUF loads and stores.

Reviewed By: dp, arsenm

Differential Revision: https://reviews.llvm.org/D137783

[AMDGPU] Add & use `hasNamedOperand`, NFC

In a lot of places, we were just calling `getNamedOperandIdx` to check if the result was != or == to -1.
This is fine in itself, but it's verbose and doesn'

[AMDGPU] Add & use `hasNamedOperand`, NFC

In a lot of places, we were just calling `getNamedOperandIdx` to check if the result was != or == to -1.
This is fine in itself, but it's verbose and doesn't make the intention clear, IMHO. I added a `hasNamedOperand` and replaced all cases I could find with regexes and manually.

Reviewed By: arsenm, foad

Differential Revision: https://reviews.llvm.org/D137540

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[AMDGPU] Make the uses_dynamic_stack field in the kernel descriptor and the metadata map specific to code object v5 and later

Unfortunately, we have a broken handling of this in the runtime of rocm

[AMDGPU] Make the uses_dynamic_stack field in the kernel descriptor and the metadata map specific to code object v5 and later

Unfortunately, we have a broken handling of this in the runtime of rocm
5.3. The runtime is expected to handle this correctly when v5 becomes
the default.

Differential Revision: https://reviews.llvm.org/D134714

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[AMDGPU] Make disassembler convertFMAanyK call more generic

Make support more generic to support future instructions.
Currently NFC.

Reviewed By: foad, arsenm

Differential Revision: https://review

[AMDGPU] Make disassembler convertFMAanyK call more generic

Make support more generic to support future instructions.
Currently NFC.

Reviewed By: foad, arsenm

Differential Revision: https://reviews.llvm.org/D135678

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[AMDGPU] Fix a warning

This patch fixes:

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:800:17:
error: unused variable 'DST_IDX' [-Werror,-Wunused-variable]

[AMDGPU][MC][GFX11] Correct v_fmac_.*_e64_dpp

Differential Revision: https://reviews.llvm.org/D134961

[AMDGPU][MC][GFX11] Disable non-null src0 for s_waitcnt_*cnt

Differential Revision: https://reviews.llvm.org/D134809

Revert "[NFC][AMDGPU] Refactor AMDGPUDisassembler"

This reverts commit f5831514612cd9e014e4fc7455b75411531fe6e1.

[NFC][AMDGPU] Refactor AMDGPUDisassembler

Clean up ahead of a patch to fix bugs in the AMDGPUDisassembler.

Use lit.local.cfg substitutions and more idiomatic use of split-file to
simplify and exten

[NFC][AMDGPU] Refactor AMDGPUDisassembler

Clean up ahead of a patch to fix bugs in the AMDGPUDisassembler.

Use lit.local.cfg substitutions and more idiomatic use of split-file to
simplify and extend existing kernel-descriptor disassembly tests.

Add a comment to AMDHSAKernelDescriptor.h, as at least one small set
towards keeping all kernel-descriptor sensitive code in sync.

Reviewed By: kzhuravl, arsenm

Differential Revision: https://reviews.llvm.org/D130105

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[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C

Due to the encoding changes in GFX11, we had a hack in place that
disables the use of VGPRs above 128. This patch removes the need for
that

[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C

Due to the encoding changes in GFX11, we had a hack in place that
disables the use of VGPRs above 128. This patch removes the need for
that hack.

We introduce a new register class VGPR_32_Lo128 which is used for 16-bit
operands of VOP1, VOP2, and VOPC instructions. This register class only has the
low 128 VGPRs, but is otherwise identical to VGPR_32. Therefore, 16-bit VOP1,
VOP2, and VOPC instructions are correctly limited to use the first 128
VGPRs, while the other instructions can freely use all 256.

We introduce new pseduo-instructions used on GFX11 which have the suffix
t16 (True 16) to use the VGPR_32_Lo128 register class.

Reviewed By: foad, rampitec, #amdgpu

Differential Revision: https://reviews.llvm.org/D133723

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