[AMDGPU] GFX12: Add Split Workgroup Barrier (#74836)

Co-authored-by: Vang Thao <Vang.Thao@amd.com>

[AMDGPU] Update IEEE and DX10_CLAMP for GFX12 (#75030)

Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>

[AMDGPU] Update VOP instructions for GFX12 (#74853)

Co-authored-by: Mirko Brkusanin <Mirko.Brkusanin@amd.com>

[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)

This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::

[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)

This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.

I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.

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[AMDGPU] Add GFX12 encoding for VINTERP instructions (#74616)

[AMDGPU] Add VEXPORT encoding for GFX12 (#74615)

In GFX12 the exp instruction is renamed to export, but exp is still
accepted as an alias.

Co-authored-by: Mateja Marjanovic <mateja.marjanovic@am

[AMDGPU] Add VEXPORT encoding for GFX12 (#74615)

In GFX12 the exp instruction is renamed to export, but exp is still
accepted as an alias.

Co-authored-by: Mateja Marjanovic <mateja.marjanovic@amd.com>

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[AMDGPU] GFX12: Add s_prefetch_inst/data instructions (#74448)

Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>

[AMDGPU] Add GFX12 encoding and aliases for existing SOP (SALU) instructions (#74305)

[AMDGPU][MC] Add GFX12 VIMAGE and VSAMPLE encodings (#74062)

AMDGPU: Minor updates to program resource registers (#69525)

- Be explicit about which program resource register is supported by
which target
- RSRC1
- FP16_OVFL is GFX9+
- WGP_M

AMDGPU: Minor updates to program resource registers (#69525)

- Be explicit about which program resource register is supported by
which target
- RSRC1
- FP16_OVFL is GFX9+
- WGP_MODE is GFX10+
- MEM_ORDERED is GFX10+
- FWD_PROGRESS is GFX10+
- RSRC3
- INST_PREF_SIZE is GFX11+
- TRAP_ON_START is GFX11+
- TRAP_ON_END is GFX11+
- IMAGE_OP is GFX11+
- Do not emit GFX11+ fields when disassembling GFX10 code objects
- Tighten enforcement of reserved bits in disassembler

---------

Co-authored-by: Konstantin Zhuravlyov <kzhuravl@amd.com>

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[AMDGPU] Change the representation of double literals in operands (#68740)

A 64-bit literal can be used as a 32-bit zero or sign extended operand.
In case of double zeroes are added to the low 32 b

[AMDGPU] Change the representation of double literals in operands (#68740)

A 64-bit literal can be used as a 32-bit zero or sign extended operand.
In case of double zeroes are added to the low 32 bits. Currently asm
parser stores only high 32 bits of a double into an operand. To support
codegen as requested by the
https://github.com/llvm/llvm-project/issues/67781 we need to change the
representation to store a full 64-bit value so that codegen can simply
add immediates to an instruction.

There is some code to support compatibility with existing tests and asm
kernels. We allow to use short hex strings to represent only a high 32
bit of a double value as a valid literal.

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[llvm] Use llvm::endianness::{big,little,native} (NFC)

Now that llvm::support::endianness has been renamed to
llvm::endianness, we can use the shorter form. This patch replaces
support::endianness:

[llvm] Use llvm::endianness::{big,little,native} (NFC)

Now that llvm::support::endianness has been renamed to
llvm::endianness, we can use the shorter form. This patch replaces
support::endianness::{big,little,native} with
llvm::endianness::{big,little,native}.

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Revert "[AMDGPU] Add [[maybe_unused]] to several unused functions (NFC)"

This reverts commit fff16807c2e6c64d671b2f6b7b3ae76f5e16e38d.

We no longer need this workaround after
053478bbd0ae5329ea7993

Revert "[AMDGPU] Add [[maybe_unused]] to several unused functions (NFC)"

This reverts commit fff16807c2e6c64d671b2f6b7b3ae76f5e16e38d.

We no longer need this workaround after
053478bbd0ae5329ea7993261225e6541f728858.

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[AMDGPU] Add [[maybe_unused]] to several unused functions (NFC)

Ivan is planning to introduce actual uses of these functions in near
future.

[AMDGPU][NFC] Add True16 operand definitions.

Reviewed By: Joe_Nash

Differential Revision: https://reviews.llvm.org/D156103

Reapply "[AMDGPU] Introduce real and keep fake True16 instructions."

Reverts 6cb3866b1ce9d835402e414049478cea82427cf1.

Analysis of failures on buildbots with expensive checks enabled showed
that th

Reapply "[AMDGPU] Introduce real and keep fake True16 instructions."

Reverts 6cb3866b1ce9d835402e414049478cea82427cf1.

Analysis of failures on buildbots with expensive checks enabled showed
that the problem was triggered by changes in another commit,
469b3bfad20550968ac428738eb1f8bb8ce3e96d, and was caused by the bug
addressed in #67245.

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Revert "[AMDGPU] Introduce real and keep fake True16 instructions."

This reverts commit 0f864c7b8bc9323293ec3d85f4bd5322f8f61b16 due to
failures on expensive checks.

[AMDGPU] Introduce real and keep fake True16 instructions.

The existing fake True16 instructions using 32-bit VGPRs are supposed to
co-exist with real ones until all the necessary True16 functionali

[AMDGPU] Introduce real and keep fake True16 instructions.

The existing fake True16 instructions using 32-bit VGPRs are supposed to
co-exist with real ones until all the necessary True16 functionality is
implemented and relevant tests are updated.

Reviewed By: arsenm, Joe_Nash

Differential Revision: https://reviews.llvm.org/D156101

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[AMDGPU] Add gfx1150 SALU Float instructions (#66884)

[AMDGPU] Add ASM and MC updates for preloading kernargs

Add assembler directives for preloading kernel arguments that correspond
to new fields in the kernel descriptor for the length and offset of
a

[AMDGPU] Add ASM and MC updates for preloading kernargs

Add assembler directives for preloading kernel arguments that correspond
to new fields in the kernel descriptor for the length and offset of
arguments that will be placed in SGPRs prior to kernel launch. Alignment
of the arguments in SGPRs is equivalent to the kernarg segment when
accessed via the kernarg_segment_ptr. Kernarg SGPRs are allocated
directly after other user SGPRs.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D159459

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[AMDGPU][MC] Fix handling of A16 operands in intersect_ray instructions.

The patch adds the support for 'noa16' operands in non-A16 variants of
the instructions, fixes validation of A16 operands and

[AMDGPU][MC] Fix handling of A16 operands in intersect_ray instructions.

The patch adds the support for 'noa16' operands in non-A16 variants of
the instructions, fixes validation of A16 operands and eliminates the
custom conversion to MCInst.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D155057

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[AMDGPU] Improve assembler + disassembler handling of kernel descriptors

* Relax the AsmParser to accept `.amdhsa_wavefront_size32 0` when the
`.amdhsa_shared_vgpr_count` directive is present.
* T

[AMDGPU] Improve assembler + disassembler handling of kernel descriptors

* Relax the AsmParser to accept `.amdhsa_wavefront_size32 0` when the
`.amdhsa_shared_vgpr_count` directive is present.
* Teach the KD disassembler to respect the setting of
KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 when calculating the
value of `.amdhsa_next_free_vgpr`.
* Teach the KD disassembler to disassemble COMPUTE_PGM_RSRC3 for gfx90a
and gfx10+.
* Include "pseudo directive" comments for gfx10 fields which are not
controlled by any assembler directive.
* Fix disassembleObject failure diagnostic in llvm-objdump to not
hard-code a comment string, and to follow the convention of not
capitalizing the first sentence.

Reviewed By: rochauha

Differential Revision: https://reviews.llvm.org/D128014

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[AMDGPU][AsmParser][NFC] Clean up the implementation of KImmFP operands.

addKImmFPOperands() duplicates the KImmFP-specific logic implemented in
addLiteralImmOperand() and therefore can be removed.

[AMDGPU][AsmParser][NFC] Clean up the implementation of KImmFP operands.

addKImmFPOperands() duplicates the KImmFP-specific logic implemented in
addLiteralImmOperand() and therefore can be removed.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D154427

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[AMDGPU][AsmParser][NFC] Simplify parsing of sopp_brtarget operands.

Also refine the definitions while there.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: mbrkusanin

[AMDGPU][AsmParser][NFC] Simplify parsing of sopp_brtarget operands.

Also refine the definitions while there.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: mbrkusanin

Differential Revision: https://reviews.llvm.org/D154061

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[NFC][AMDGPU] Refactor AMDGPUDisassembler

Clean up ahead of a patch to fix bugs in the AMDGPUDisassembler.

Use split-file to simplify and extend existing kernel-descriptor
disassembly tests.

Add a

[NFC][AMDGPU] Refactor AMDGPUDisassembler

Clean up ahead of a patch to fix bugs in the AMDGPUDisassembler.

Use split-file to simplify and extend existing kernel-descriptor
disassembly tests.

Add a comment to AMDHSAKernelDescriptor.h, as at least one small set
towards keeping all kernel-descriptor sensitive code in sync.

Reviewed By: MaskRay, kzhuravl, arsenm

Differential Revision: https://reviews.llvm.org/D130105

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