#
bee79cdc |
| 15-Sep-2020 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
SelectionDAGBuilder.h - remove unnecessary includes. NFCI.
Reduce to forward declarations and move implicit dependencies down to the cpp files.
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#
c193a689 |
| 14-Sep-2020 |
Craig Topper <craig.topper@intel.com> |
[SelectionDAG] Use Align/MaybeAlign in calls to getLoad/getStore/getExtLoad/getTruncStore.
The versions that take 'unsigned' will be removed in the future.
I tried to use getOriginalAlign instead o
[SelectionDAG] Use Align/MaybeAlign in calls to getLoad/getStore/getExtLoad/getTruncStore.
The versions that take 'unsigned' will be removed in the future.
I tried to use getOriginalAlign instead of getAlign in some places. getAlign factors in the minimum alignment implied by the offset in the pointer info. Since we're also passing the pointer info we can use the original alignment.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D87592
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#
844e94a5 |
| 08-Sep-2020 |
Craig Topper <craig.topper@intel.com> |
[SelectionDAGBuilder] Remove Unnecessary FastMathFlags temporary. Use SDNodeFlags instead. NFCI
This was a missed simplication in D87200
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#
b1e68f88 |
| 08-Sep-2020 |
Craig Topper <craig.topper@intel.com> |
[SelectionDAGBuilder] Pass fast math flags to getNode calls rather than trying to set them after the fact.:
This removes the after the fact FMF handling from D46854 in favor of passing fast math fla
[SelectionDAGBuilder] Pass fast math flags to getNode calls rather than trying to set them after the fact.:
This removes the after the fact FMF handling from D46854 in favor of passing fast math flags to getNode. This should be a superset of D87130.
This required adding a SDNodeFlags to SelectionDAG::getSetCC.
Now we manage to contant fold some stuff undefs during the initial getNode that we don't do in later DAG combines.
Differential Revision: https://reviews.llvm.org/D87200
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#
714ceefa |
| 31-Aug-2020 |
Jonas Paulsson <paulsson@linux.vnet.ibm.com> |
[SelectionDAG] Always intersect SDNode flags during getNode() node memoization.
Previously SDNodeFlags::instersectWith(Flags) would do nothing if Flags was in an undefined state, which is very bad g
[SelectionDAG] Always intersect SDNode flags during getNode() node memoization.
Previously SDNodeFlags::instersectWith(Flags) would do nothing if Flags was in an undefined state, which is very bad given that this is the default when getNode() is called without passing an explicit SDNodeFlags argument.
This meant that if an already existing and reused node had a flag which the second caller to getNode() did not set, that flag would remain uncleared.
This was exposed by https://bugs.llvm.org/show_bug.cgi?id=47092, where an NSW flag was incorrectly set on an add instruction (which did in fact overflow in one of the two original contexts), so when SystemZElimCompare removed the compare with 0 trusting that flag, wrong-code resulted.
There is more that needs to be done in this area as discussed here:
Differential Revision: https://reviews.llvm.org/D86871
Review: Ulrich Weigand, Sanjay Patel
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f4257c58 |
| 14-Aug-2020 |
David Sherwood <david.sherwood@arm.com> |
[SVE] Make ElementCount members private
This patch changes ElementCount so that the Min and Scalable members are now private and can only be accessed via the get functions getKnownMinValue() and isS
[SVE] Make ElementCount members private
This patch changes ElementCount so that the Min and Scalable members are now private and can only be accessed via the get functions getKnownMinValue() and isScalable(). In addition I've added some other member functions for more commonly used operations. Hopefully this makes the class more useful and will reduce the need for calling getKnownMinValue().
Differential Revision: https://reviews.llvm.org/D86065
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#
3d943bcd |
| 27-Aug-2020 |
Lucas Prates <lucas.prates@arm.com> |
[CodeGen] Properly propagating Calling Convention information when lowering vector arguments
When joining the legal parts of vector arguments into its original value during the lower of Formal Argum
[CodeGen] Properly propagating Calling Convention information when lowering vector arguments
When joining the legal parts of vector arguments into its original value during the lower of Formal Arguments in SelectionDAGBuilder, the Calling Convention information was not being propagated for the handling of each individual parts. The same did not happen when lowering calls, causing a mismatch.
This patch fixes the issue by properly propagating the Calling Convention details.
This fixes Bugzilla #47001.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D86715
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#
72305a08 |
| 26-Aug-2020 |
aartbik <ajcbik@google.com> |
[llvm] [DAG] Fix bug in llvm.get.active.lane.mask lowering
This intrinsic only accepted proper machine vector lengths. Fixed by this change. With unit tests.
https://bugs.llvm.org/show_bug.cgi?id=4
[llvm] [DAG] Fix bug in llvm.get.active.lane.mask lowering
This intrinsic only accepted proper machine vector lengths. Fixed by this change. With unit tests.
https://bugs.llvm.org/show_bug.cgi?id=47299
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D86585
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39522b1e |
| 25-Aug-2020 |
Sjoerd Meijer <sjoerd.meijer@arm.com> |
[SelectionDAG] Legalize intrinsic get.active.lane.mask
This adapts legalization of intrinsic get.active.lane.mask to the new semantics as described in D86147. Because the second argument is now the
[SelectionDAG] Legalize intrinsic get.active.lane.mask
This adapts legalization of intrinsic get.active.lane.mask to the new semantics as described in D86147. Because the second argument is now the loop tripcount, we legalize this intrinsic to an 'icmp ULT' instead of an ULE when it was the backedge-taken count.
Differential Revision: https://reviews.llvm.org/D86302
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#
0819a641 |
| 31-Mar-2020 |
Jay Foad <jay.foad@amd.com> |
[SelectionDAG] Better legalization for FSHL and FSHR
In SelectionDAGBuilder always translate the fshl and fshr intrinsics to FSHL and FSHR (or ROTL and ROTR) instead of lowering them to shifts and O
[SelectionDAG] Better legalization for FSHL and FSHR
In SelectionDAGBuilder always translate the fshl and fshr intrinsics to FSHL and FSHR (or ROTL and ROTR) instead of lowering them to shifts and ORs. Improve the legalization of FSHL and FSHR to avoid code quality regressions.
Differential Revision: https://reviews.llvm.org/D77152
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#
a407ec9b |
| 19-Aug-2020 |
Mehdi Amini <joker.eph@gmail.com> |
Revert "Revert "[NFC][llvm] Make the contructors of `ElementCount` private.""
Was reverted because MLIR/Flang builds were broken, these APIs have been fixed in the meantime.
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4fc56d70 |
| 19-Aug-2020 |
Mehdi Amini <joker.eph@gmail.com> |
Revert "[NFC][llvm] Make the contructors of `ElementCount` private."
This reverts commit 264afb9e6aebc98c353644dd0700bec808501cab. (and dependent 6b742cc48 and fc53bd610f)
MLIR/Flang are broken.
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264afb9e |
| 17-Aug-2020 |
Francesco Petrogalli <francesco.petrogalli@arm.com> |
[NFC][llvm] Make the contructors of `ElementCount` private.
Differential Revision: https://reviews.llvm.org/D86120
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85c7e89f |
| 11-Aug-2020 |
Kerry McLaughlin <kerry.mclaughlin@arm.com> |
[CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize
Changes the Offset arguments to both functions from int64_t to TypeSize & updates all uses of the functions to creat
[CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize
Changes the Offset arguments to both functions from int64_t to TypeSize & updates all uses of the functions to create the offset using TypeSize::Fixed()
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D85220
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#
5de6c56f |
| 16-Jul-2020 |
Bevin Hansson <bevin.hansson@ericsson.com> |
[Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.
Summary: This patch adds two intrinsics, llvm.sshl.sat and llvm.ushl.sat, which perform signed and unsigned saturating left shift, resp
[Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.
Summary: This patch adds two intrinsics, llvm.sshl.sat and llvm.ushl.sat, which perform signed and unsigned saturating left shift, respectively.
These are useful for implementing the Embedded-C fixed point support in Clang, originally discussed in http://lists.llvm.org/pipermail/llvm-dev/2018-August/125433.html and http://lists.llvm.org/pipermail/cfe-dev/2018-May/058019.html
Reviewers: leonardchan, craig.topper, bjope, jdoerfert
Subscribers: hiraditya, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D83216
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28e322ea |
| 16-Jul-2020 |
Jay Foad <jay.foad@amd.com> |
[PowerPC] Custom lowering for funnel shifts
The custom lowering saves an instruction over the generic expansion, by taking advantage of the fact that PowerPC shift instructions are well defined in t
[PowerPC] Custom lowering for funnel shifts
The custom lowering saves an instruction over the generic expansion, by taking advantage of the fact that PowerPC shift instructions are well defined in the shift-by-bitwidth case.
Differential Revision: https://reviews.llvm.org/D83948
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31c7a2fd |
| 03-Aug-2020 |
Cameron McInally <mcinally@cray.com> |
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
This patch stops unconditionally transforming FSUB(-0,X) into an FNEG(X) while building the DAG. There is also one small change to
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
This patch stops unconditionally transforming FSUB(-0,X) into an FNEG(X) while building the DAG. There is also one small change to handle the new FSUB(-0,X) similarly to FNEG(X) in the AMDGPU backend.
Differential Revision: https://reviews.llvm.org/D84056
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Revision tags: llvmorg-10.0.0-rc1, llvmorg-11-init, llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1, llvmorg-9.0.0, llvmorg-9.0.0-rc6, llvmorg-9.0.0-rc5, llvmorg-9.0.0-rc4, llvmorg-9.0.0-rc3, llvmorg-9.0.0-rc2, llvmorg-9.0.0-rc1, llvmorg-10-init, llvmorg-8.0.1, llvmorg-8.0.1-rc4, llvmorg-8.0.1-rc3, llvmorg-8.0.1-rc2, llvmorg-8.0.1-rc1, llvmorg-8.0.0, llvmorg-8.0.0-rc5, llvmorg-8.0.0-rc4, llvmorg-8.0.0-rc3, llvmorg-7.1.0, llvmorg-7.1.0-rc1, llvmorg-8.0.0-rc2, llvmorg-8.0.0-rc1, llvmorg-7.0.1, llvmorg-7.0.1-rc3, llvmorg-7.0.1-rc2, llvmorg-7.0.1-rc1, llvmorg-7.0.0, llvmorg-7.0.0-rc3, llvmorg-7.0.0-rc2, llvmorg-7.0.0-rc1, llvmorg-6.0.1, llvmorg-6.0.1-rc3, llvmorg-6.0.1-rc2, llvmorg-6.0.1-rc1, llvmorg-5.0.2, llvmorg-5.0.2-rc2, llvmorg-5.0.2-rc1, llvmorg-6.0.0, llvmorg-6.0.0-rc3, llvmorg-6.0.0-rc2, llvmorg-6.0.0-rc1, llvmorg-5.0.1, llvmorg-5.0.1-rc3, llvmorg-5.0.1-rc2, llvmorg-5.0.1-rc1, llvmorg-5.0.0, llvmorg-5.0.0-rc5, llvmorg-5.0.0-rc4, llvmorg-5.0.0-rc3, llvmorg-5.0.0-rc2, llvmorg-5.0.0-rc1, llvmorg-4.0.1, llvmorg-4.0.1-rc3, llvmorg-4.0.1-rc2, llvmorg-4.0.1-rc1, llvmorg-4.0.0, llvmorg-4.0.0-rc4, llvmorg-4.0.0-rc3, llvmorg-4.0.0-rc2, llvmorg-4.0.0-rc1, llvmorg-3.9.1, llvmorg-3.9.1-rc3, llvmorg-3.9.1-rc2, llvmorg-3.9.1-rc1, llvmorg-3.9.0, llvmorg-3.9.0-rc3, llvmorg-3.9.0-rc2, llvmorg-3.9.0-rc1, llvmorg-3.8.1, llvmorg-3.8.1-rc1 |
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#
57bd64ff |
| 27-May-2016 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Support addrspacecast initializers with isNoopAddrSpaceCast
Moves isNoopAddrSpaceCast to the TargetMachine. It logically belongs with the DataLayout.
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b0eb40ca |
| 31-Jul-2020 |
Vitaly Buka <vitalybuka@google.com> |
[NFC] Remove unused GetUnderlyingObject paramenter
Depends on D84617.
Differential Revision: https://reviews.llvm.org/D84621
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89051eba |
| 31-Jul-2020 |
Vitaly Buka <vitalybuka@google.com> |
[NFC] GetUnderlyingObject -> getUnderlyingObject
I am going to touch them in the next patch anyway
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afae6d97 |
| 29-Jul-2020 |
Jon Roelofs <jonathan_roelofs@apple.com> |
[SelectionDAG] Fix lowering of vector geps
This fixes an assertion failure that was being triggered in SelectionDAG::getZeroExtendInReg(), where it was trying to extend the <2xi32> to i64 (which sho
[SelectionDAG] Fix lowering of vector geps
This fixes an assertion failure that was being triggered in SelectionDAG::getZeroExtendInReg(), where it was trying to extend the <2xi32> to i64 (which should have been <2xi64>).
Fixes: rdar://66016901
Differential Revision: https://reviews.llvm.org/D84884
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deb4bb2b |
| 19-Jul-2020 |
Nikita Popov <nikita.ppv@gmail.com> |
[IR] Add min/max/abs intrinsics
This adds the llvm.abs(), llvm.umin(), llvm.umax(), llvm.smin(), and llvm.smax() intrinsics specified in D81829. For SelectionDAG, the ISD opcodes and all the legaliz
[IR] Add min/max/abs intrinsics
This adds the llvm.abs(), llvm.umin(), llvm.umax(), llvm.smin(), and llvm.smax() intrinsics specified in D81829. For SelectionDAG, the ISD opcodes and all the legalization and lowering already exist, so this just wires them up to the intrinsic in the SDAG builder and adds rudimentary tests. For GlobalISel only the min/max intrinsics are wired up, as llvm.abs() will require the addition of a G_ABS op, and corresponding legalization support.
Differential Revision: https://reviews.llvm.org/D84125
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fa956882 |
| 22-Jul-2020 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
SelectionDAGBuilder.cpp - remove duplicate includes that already exist in SelectionDAGBuilder.h. NFC.
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f659c440 |
| 25-Jun-2020 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
CodeGen: Add support for lowering byref attribute
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023883a8 |
| 29-Jun-2020 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
IR: Rename Argument::hasPassPointeeByValueAttr to prepare for byref
When the byref attribute is added, there will need to be two similar functions for the existing cases which have an associate valu
IR: Rename Argument::hasPassPointeeByValueAttr to prepare for byref
When the byref attribute is added, there will need to be two similar functions for the existing cases which have an associate value copy, and byref which does not. Most, but not all of the existing uses will use the existing version.
The associated size function added by D82679 also needs to contextually differ, and will help eliminate a few places still relying on pointee element types.
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