Emit a more efficient magic number multiplication for exact sdivs.

We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.

struct foo { char x[24];

Emit a more efficient magic number multiplication for exact sdivs.

We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.

struct foo { char x[24]; };
long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
movl 4(%esp), %eax
subl 8(%esp), %eax
sarl $3, %eax
imull $-1431655765, %eax, %eax
instead of
movl 4(%esp), %eax
subl 8(%esp), %eax
movl $715827883, %ecx
imull %ecx
movl %edx, %eax
shrl $31, %eax
sarl $2, %edx
addl %eax, %edx
movl %edx, %eax

llvm-svn: 134695

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Introduce "expect" intrinsic instructions.

llvm-svn: 134516

Remove getRegClassForInlineAsmConstraint and all dependencies.

Fixes rdar://9643582

llvm-svn: 134123

Distinguish early clobber output operands from clobbered registers.

Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.

The new Kind_Clobb

Distinguish early clobber output operands from clobbered registers.

Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.

The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.

This will pop a register off the stack:

asm("fstp %st" : : "t"(x) : "st");

While this will pop the input and push an output:

asm("fst %st" : "=&t"(r) : "t"(x));

We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.

llvm-svn: 133902

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When promoting the vector elements in CopyToParts, use vector trunc
instead of scalarizing, and doing an element-by-element truncat.

llvm-svn: 133382

Introduce MachineBranchProbabilityInfo class, which has similar API to
BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn

Introduce MachineBranchProbabilityInfo class, which has similar API to
BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn off this analysis
set -use-mbpi=false.

llvm-svn: 133184

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Add TargetRegisterInfo::getRawAllocationOrder().

This virtual function will replace allocation_order_begin/end as the one
to override when implementing custom allocation orders. It is simpler to
hav

Add TargetRegisterInfo::getRawAllocationOrder().

This virtual function will replace allocation_order_begin/end as the one
to override when implementing custom allocation orders. It is simpler to
have one function return an ArrayRef than having two virtual functions
computing different ends of the same array.

Use getRawAllocationOrder() in place of allocation_order_begin() where
it makes sense, but leave some clients that look like they really want
the filtered allocation orders from RegisterClassInfo.

llvm-svn: 133170

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Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach
autoupgrade.

llvm-svn: 132976

Improve the generated code by getCopyFromPartsVector for promoted integer types.
Instead of scalarizing, and doing an element-by-element truncat, use vector
truncate.
Add support for scalarization of

Improve the generated code by getCopyFromPartsVector for promoted integer types.
Instead of scalarizing, and doing an element-by-element truncat, use vector
truncate.
Add support for scalarization of vectors: i8 -> <1 x i1> (from Duncan's
testcase).

llvm-svn: 132892

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Add a parameter to CCState so that it can access the MachineFunction.

No functional change.

Part of PR6965

llvm-svn: 132763

TypeLegalizer: Add support for passing of vector-promoted types in registers (copyFromParts/copyToParts).

llvm-svn: 132649

Add a TODO about memory operands.

llvm-svn: 132559

Have LowerOperandForConstraint handle multiple character constraints.

Part of rdar://9119939

llvm-svn: 132510

Allow bitcasts between valid types of the same size and vector
types if the vector type is legal.

Fixes rdar://9306086

llvm-svn: 132420

Preserve debug info during iSel by keeping DanglingDebugInfoMap live until end of function.
Patch by Micah Villmow

llvm-svn: 131908

Eliminate some temporary variables, and don't call getByValTypeAlignment
when we're just going to throw the result away. No functionality change.

llvm-svn: 131880

Preserve debug info for unused zero extended boolean argument.
Radar 9422775.

llvm-svn: 131422

Make codegen able to handle values of empty types. This is one way
to fix PR9900. I will keep it open until sable is able to comment on it.

llvm-svn: 131294

Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it

Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>

llvm-svn: 131174

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Disable my little CopyToReg argument hack with fast-isel. rdar://problem/9413587 .

llvm-svn: 131156

Look through struct wrapped types for inline asm statments.

Patch by Evan Cheng.

llvm-svn: 131093

80 col violations.

llvm-svn: 131015

Avoid extra vreg copies for arguments passed in registers. Specifically, this can make MachineCSE more effective in some cases (especially in small functions). PR8361 / part of rdar://problem/82594

Avoid extra vreg copies for arguments passed in registers. Specifically, this can make MachineCSE more effective in some cases (especially in small functions). PR8361 / part of rdar://problem/8259436 .

llvm-svn: 130928

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A dbg.declare may not be in entry block, even if it is referring to an incoming argument. However, It is appropriate to emit DBG_VALUE referring to this incoming argument in entry block in MachineFun

A dbg.declare may not be in entry block, even if it is referring to an incoming argument. However, It is appropriate to emit DBG_VALUE referring to this incoming argument in entry block in MachineFunction.

llvm-svn: 130129

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Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!

llvm-svn: 129558