Fix a bunch of unused variable warnings when doing a release
build with gcc-4.6.

llvm-svn: 142350

Fix comment to refer to correct instruction

llvm-svn: 142334

Clear out the landing pad to call site map for each function.

This isn't put into the 'clear()' method because the information needs to stick
around (at least for a little bit) after the selection D

Clear out the landing pad to call site map for each function.

This isn't put into the 'clear()' method because the information needs to stick
around (at least for a little bit) after the selection DAG is built.

llvm-svn: 142032

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Encode register class constreaints in inline asm instructions.

The inline asm operand constraint is initially encoded in the virtual
register for the operand, but that register class may change duri

Encode register class constreaints in inline asm instructions.

The inline asm operand constraint is initially encoded in the virtual
register for the operand, but that register class may change during
coalescing, and the original constraint is lost.

Encode the original register class as part of the flag word for each
inline asm operand. This makes it possible to recover the actual
constraint required by inline asm, just like we can for normal
instructions.

llvm-svn: 141833

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Use a utility from MathExtras to clarify a check and avoid undefined behavior. Based on patch by Ahmed Charles.

llvm-svn: 141829

Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
do. This will be useful later on with the new SJLJ stuff.

llvm-svn: 141416

Remove the old atomic instrinsics. autoupgrade functionality is included with this patch.

llvm-svn: 141333

Modify the mapping from landing pad to call sites to accept more than one call
site.

llvm-svn: 141226

Create a mapping between the landing pad basic block and the call site index for later use.

llvm-svn: 141125

Promote comment to doxycomment. Adjust whitespace. No functionality change.

llvm-svn: 140899

Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy.

llvm-svn: 140803

Use the local we already set up.

llvm-svn: 140745

Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.

llvm-svn: 140678

Create and use an llvm.eh.sjlj.functioncontext intrinsic.

This intrinsic is used to pass the index of the function context to the back-end
for further processing. The back-end is in charge of fillin

Create and use an llvm.eh.sjlj.functioncontext intrinsic.

This intrinsic is used to pass the index of the function context to the back-end
for further processing. The back-end is in charge of filling in the rest of the
entries.

llvm-svn: 140676

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Fix check for unaligned load/store so it doesn't catch over-aligned load/store.

llvm-svn: 139649

Error out on CodeGen of unaligned load/store. Fix test so it isn't accidentally testing that case.

llvm-svn: 139641

tidy up a bit

llvm-svn: 139419

Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.

ll

Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.

llvm-svn: 139330

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Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them w

Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.

llvm-svn: 139159

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Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting

Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.

llvm-svn: 139140

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Atomic load/store on ARM/Thumb.

I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-wit

Atomic load/store on ARM/Thumb.

I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.

llvm-svn: 138621

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Basic x86 code generation for atomic load and store instructions.

llvm-svn: 138478

Fix 80 col violations.

llvm-svn: 138356

Add the support in code-gen for the landingpad instruction lowering.

The landingpad instruction is lowered into the EXCEPTIONADDR and EHSELECTION
SDNodes. The information from the landingpad instruc

Add the support in code-gen for the landingpad instruction lowering.

The landingpad instruction is lowered into the EXCEPTIONADDR and EHSELECTION
SDNodes. The information from the landingpad instruction is harvested by the
'AddLandingPadInfo' function. The new EH uses the current EH scheme in the
back-end. This will change once we switch over to the new scheme. (Reviewed by
Jakob!)

llvm-svn: 137880

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Revert patch. Forgot a dependent commit.

llvm-svn: 137875