Turn avx2 vinserti128 intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove patterns for selecting the intrinsic. Similar was already done for avx1.

llvm-svn: 154272

Remove 'else' after 'if' that ends in return.

llvm-svn: 154267

Teach CodeGen's version of computeMaskedBits to understand the range metadata.
This is the CodeGen equivalent of r153747. I tested that there is not noticeable
performance difference with any combina

Teach CodeGen's version of computeMaskedBits to understand the range metadata.
This is the CodeGen equivalent of r153747. I tested that there is not noticeable
performance difference with any combination of -O0/-O2 /-g when compiling
gcc as a single compilation unit.

llvm-svn: 153817

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More debug output.

llvm-svn: 153571

Add a debug statement.

llvm-svn: 153428

Assign node orders to target intrinsics which do not produce results. rdar://11096639

llvm-svn: 153269

Add another debug statement.

llvm-svn: 152843

llvm::SwitchInst
Renamed methods caseBegin, caseEnd and caseDefault with case_begin, case_end, and case_default.
Added some notes relative to case iterators.

llvm-svn: 152532

Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html

Implemented CaseIterator and it solves almost

Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html

Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*".

ConstCaseIt is just a read-only iterator.
CaseIt is read-write iterator; it allows to change case successor and case value.

Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters.

Main way of iterator usage looks like this:
SwitchInst *SI = ... // intialize it somehow

for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) {
BasicBlock *BB = i.getCaseSuccessor();
ConstantInt *V = i.getCaseValue();
// Do something.
}

If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method.
If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method.

There are also related changes in llvm-clients: klee and clang.

llvm-svn: 152297

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Fix warnings about adding a bool to a string.
Patch by Sean Silva!

llvm-svn: 152042

Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even though they could have sideeffects.

Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone".

Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even though they could have sideeffects.

Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone".

llvm-svn: 151807

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Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.

llvm-svn: 151645

Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.

llvm-svn: 151630

Code cleanup following CR by Duncan.

llvm-svn: 151627

Fix a bug in the code that builds SDNodes from vector GEPs.

When the GEP index is a vector of pointers, the code that calculated the size
of the element started from the vector type, and not the con

Fix a bug in the code that builds SDNodes from vector GEPs.

When the GEP index is a vector of pointers, the code that calculated the size
of the element started from the vector type, and not the contained pointer type.
As a result, instead of looking at the data element pointed by the vector, this
code used the size of the vector. This works for 32bit members (on 32bit
systems), but not for other types. Added code to peel the vector type and
added a test.

llvm-svn: 151626

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Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the i

Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299

llvm-svn: 151623

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SDAGBuilder: Remove register sets that were never read and prune dead code surrounding it.

llvm-svn: 151364

Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics

llvm-svn: 151342

If the Address of a variable is an argument then treat the entire
variable declaration as an argument because we want that address
anyhow for our debug information.

This seems to fix rdar://9965111,

If the Address of a variable is an argument then treat the entire
variable declaration as an argument because we want that address
anyhow for our debug information.

This seems to fix rdar://9965111, at least we have more debug
information than before and from reading the assembly it appears
to be the correct location.

llvm-svn: 151335

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Allow an integer to be converted into an MMX type when it's used in an inline
asm.
<rdar://problem/10106006>

llvm-svn: 151303

More newline cleanups.

llvm-svn: 151235

Add some handy-dandy newlines.

llvm-svn: 151234

Properly emit _fltused with FastISel. Refactor to share code with SDAG.
Patch by Joe Groff!

llvm-svn: 151183

Rename getExceptionAddressRegister() to getExceptionPointerRegister() for consistency with setExceptionPointerRegister(...).

llvm-svn: 150460

Don't reserve the R0 and R1 registers here. We don't use these registers, and
marking them as "live-in" into a BB ruins some invariants that the back-end
tries to maintain.

llvm-svn: 150437