History log of /llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (Results 1526 – 1550 of 2094)
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# 029af150 30-Jul-2013 Eric Christopher <echristo@gmail.com>

Reflow this to be easier to read.

llvm-svn: 187459


# facc9f4e 10-Jul-2013 Adrian Prantl <aprantl@apple.com>

Document a known limitation of the status quo.

llvm-svn: 185992


# 418d1d1e 09-Jul-2013 Adrian Prantl <aprantl@apple.com>

Reapply an improved version of r180816/180817.

Change the informal convention of DBG_VALUE machine instructions so that
we can express a register-indirect address with an offset of 0.
The old conven

Reapply an improved version of r180816/180817.

Change the informal convention of DBG_VALUE machine instructions so that
we can express a register-indirect address with an offset of 0.
The old convention was that a DBG_VALUE is a register-indirect value if
the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE
is register-indirect if the first operand is a register and the second
operand is an immediate. For plain register values the combination reg,
reg is used. MachineInstrBuilder::BuildMI knows how to build the new
DBG_VALUES.

rdar://problem/13658587

llvm-svn: 185966

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# 73de7bf5 09-Jul-2013 Stephen Lin <stephenwlin@gmail.com>

AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmula

AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:

1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.

2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.

3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.

The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.

llvm-svn: 185956

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Revision tags: llvmorg-3.3.1-rc1
# cfe7f352 08-Jul-2013 Stephen Lin <stephenwlin@gmail.com>

Remove trailing whitespace from SelectionDAG/*.cpp

llvm-svn: 185780


# 6d715e86 06-Jul-2013 Stephen Lin <stephenwlin@gmail.com>

SelectionDAGBuilder: style fixes (add space between end parentheses and open brace)

llvm-svn: 185768


# dab4db53 06-Jul-2013 Tim Northover <tnorthover@apple.com>

Stop putting operations after a tail call.

This prevents the emission of DAG-generated vreg definitions after a
tail call be dropping them entirely (on the grounds that nothing could
use them anyway

Stop putting operations after a tail call.

This prevents the emission of DAG-generated vreg definitions after a
tail call be dropping them entirely (on the grounds that nothing could
use them anyway, and they interfere with O0 CodeGen).

llvm-svn: 185754

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# fee2a202 04-Jul-2013 Jakob Stoklund Olesen <stoklund@2pi.dk>

Simplify landing pad lowering.

Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that neve

Simplify landing pad lowering.

Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that never worked properly because the
CopyFromReg node weren't guaranteed to be scheduled at the top of the
basic block.

This meant the exception pointer and selector registers could be
clobbered before being copied to a virtual register.

This patch copies the two physical registers to virtual registers at
the beginning of the basic block, and lowers the landingpad instruction
directly to two CopyFromReg nodes reading the *virtual* registers. This
is safe because virtual registers don't get clobbered.

A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION
nodes.

llvm-svn: 185617

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# a1f5b901 04-Jul-2013 Jakob Stoklund Olesen <stoklund@2pi.dk>

Revert r185595-185596 which broke buildbots.

Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

llvm-svn: 185600


# fa6a7b9b 03-Jul-2013 Jakob Stoklund Olesen <stoklund@2pi.dk>

Simplify landing pad lowering.

Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that neve

Simplify landing pad lowering.

Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that never worked properly because the
CopyFromReg node weren't guaranteed to be scheduled at the top of the
basic block.

This meant the exception pointer and selector registers could be
clobbered before being copied to a virtual register.

This patch copies the two physical registers to virtual registers at
the beginning of the basic block, and lowers the landingpad instruction
directly to two CopyFromReg nodes reading the *virtual* registers. This
is safe because virtual registers don't get clobbered.

A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION
nodes.

llvm-svn: 185595

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# e1c1d363 03-Jul-2013 Craig Topper <craig.topper@gmail.com>

Use SmallVectorImpl instead of SmallVector for iterators and references to avoid specifying the vector size unnecessarily.

llvm-svn: 185512


# 983a16c0 28-Jun-2013 Manman Ren <mren@apple.com>

Debug Info: clean up usage of Verify.

No functionality change.
It should suffice to check the type of a debug info metadata, instead of
calling Verify. For cases where we know the type of a DI metad

Debug Info: clean up usage of Verify.

No functionality change.
It should suffice to check the type of a debug info metadata, instead of
calling Verify. For cases where we know the type of a DI metadata, use
assert.

Also update testing cases to make them conform to the format of DI classes.

llvm-svn: 185135

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# a3cd3502 19-Jun-2013 Bill Wendling <isanbard@gmail.com>

Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.

llvm-svn: 184360


# b51a6868 18-Jun-2013 Quentin Colombet <qcolombet@apple.com>

During SelectionDAG building explicitly set a node to constant zero when the
value is zero.
This allows optmizations to kick in more easily.
Fix some test cases so that they remain meaningful (i.e.,

During SelectionDAG building explicitly set a node to constant zero when the
value is zero.
This allows optmizations to kick in more easily.
Fix some test cases so that they remain meaningful (i.e., not completely dead
coded) when optimizations apply.

<rdar://problem/14096009> superfluous multiply by high part of zero-extended
value.

llvm-svn: 184222

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# 0252265b 16-Jun-2013 David Blaikie <dblaikie@gmail.com>

Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions

Rather than using the full power of target-specific addressing modes in
DBG_VALUEs with Frame Indicies, simply use Frame I

Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions

Rather than using the full power of target-specific addressing modes in
DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This
reduces the complexity of debug info handling down to two
representations of values (reg+offset and frame index+offset) rather
than three or four.

Ideally we could ensure that frame indicies had been eliminated by the
time we reached an assembly or dwarf generation, but I haven't spent the
time to figure out where the FIs are leaking through into that & whether
there's a good place to convert them. Some FI+offset=>reg+offset
conversion is done (see PrologEpilogInserter, for example) which is
necessary for some SelectionDAG assumptions about registers, I believe,
but it might be possible to make this a more thorough conversion &
ensure there are no remaining FIs no matter how instruction selection
is performed.

llvm-svn: 184066

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Revision tags: llvmorg-3.3.0
# f7719085 06-Jun-2013 Bill Wendling <isanbard@gmail.com>

Cache the TargetLowering info object as a pointer.

Caching it as a pointer allows us to reset it if the TargetMachine object
changes.

llvm-svn: 183361


Revision tags: llvmorg-3.3.0-rc3
# 048f99de 27-May-2013 Preston Gurd <preston.gurd@intel.com>

Convert sqrt functions into sqrt instructions when -ffast-math is in effect.

When -ffast-math is in effect (on Linux, at least), clang defines
__FINITE_MATH_ONLY__ > 0 when including <math.h>. This

Convert sqrt functions into sqrt instructions when -ffast-math is in effect.

When -ffast-math is in effect (on Linux, at least), clang defines
__FINITE_MATH_ONLY__ > 0 when including <math.h>. This causes the
preprocessor to include <bits/math-finite.h>, which renames the sqrt functions.
For instance, "sqrt" is renamed as "__sqrt_finite".

This patch adds the 3 new names in such a way that they will be treated
as equivalent to their respective original names.

llvm-svn: 182739

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# e2431c64 25-May-2013 Andrew Trick <atrick@apple.com>

Track IR ordering of SelectionDAG nodes 3/4.

Remove the old IR ordering mechanism and switch to new one. Fix unit
test failures.

llvm-svn: 182704


# ef9de2a7 25-May-2013 Andrew Trick <atrick@apple.com>

Track IR ordering of SelectionDAG nodes 2/4.

Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

llvm-svn: 182703


# 175143bf 25-May-2013 Andrew Trick <atrick@apple.com>

Track IR ordering of SelectionDAG nodes 1/4.

Use a field in the SelectionDAGNode object to track its IR ordering.
This adds fields and utility classes without changing existing
interfaces or functio

Track IR ordering of SelectionDAG nodes 1/4.

Use a field in the SelectionDAGNode object to track its IR ordering.
This adds fields and utility classes without changing existing
interfaces or functionality.

llvm-svn: 182701

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# df1ecbd7 24-May-2013 Michael J. Spencer <bigcheesegs@gmail.com>

Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.

llvm-svn: 182680


Revision tags: llvmorg-3.3.0-rc2
# 0d1e5592 22-May-2013 Adrian Prantl <aprantl@apple.com>

Unify formatting of debug output.

llvm-svn: 182495


# fff1f5f5 21-May-2013 Justin Holewinski <jholewinski@nvidia.com>

Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.

The intrinsic calls are dropped, but the annotated value is propagated.

Fixes PR 15253

Original patch by Zeng Bin!

llvm-s

Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.

The intrinsic calls are dropped, but the annotated value is propagated.

Fixes PR 15253

Original patch by Zeng Bin!

llvm-svn: 182387

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# 75865923 18-May-2013 Matt Arsenault <Matthew.Arsenault@amd.com>

Add LLVMContext argument to getSetCCResultType

llvm-svn: 182180


# 9c93059a 16-May-2013 Adrian Prantl <aprantl@apple.com>

Generate debug info for by-value struct args even if they are not used.
radar://problem/13865940

llvm-svn: 182062


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