History log of /llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (Results 1076 – 1100 of 2094)
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# b1f0a0f4 14-Sep-2016 Sanjay Patel <spatel@rotateright.com>

getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCI

llvm-svn: 281493


# adbf09e8 11-Sep-2016 Justin Lebar <jlebar@google.com>

[CodeGen] Split out the notions of MI invariance and MI dereferenceability.

Summary:
An IR load can be invariant, dereferenceable, neither, or both. But
currently, MI's notion of invariance is IR-i

[CodeGen] Split out the notions of MI invariance and MI dereferenceability.

Summary:
An IR load can be invariant, dereferenceable, neither, or both. But
currently, MI's notion of invariance is IR-invariant &&
IR-dereferenceable.

This patch splits up the notions of invariance and dereferenceability at
the MI level. It's NFC, so adds some probably-unnecessary
"is-dereferenceable" checks, which we can remove later if desired.

Reviewers: chandlerc, tstellarAMD

Subscribers: jholewinski, arsenm, nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D23371

llvm-svn: 281151

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# c6a61449 08-Sep-2016 James Molloy <james.molloy@arm.com>

[SDAGBuilder] Don't create a binary tree for switches in minsize mode

This bloats codesize - all of the non-leaf nodes are extra code.

llvm-svn: 280932


# 356f79d5 01-Sep-2016 Aditya Kumar <hiraditya@msn.com>

[SelectionDAGBuilder] Add const to relevant places

Reviewers: hans, evandro, sebpop

Differential Revision: https://reviews.llvm.org/D24112

llvm-svn: 280430


# 5f17d08f 01-Sep-2016 Michael Kuperstein <mkuper@google.com>

[SelectionDAG] Generate vector_shuffle nodes for undersized result vector sizes

Prior to this, we could generate a vector_shuffle from an IR shuffle when the
size of the result was exactly the sum o

[SelectionDAG] Generate vector_shuffle nodes for undersized result vector sizes

Prior to this, we could generate a vector_shuffle from an IR shuffle when the
size of the result was exactly the sum of the sizes of the input vectors.
If the output vector was narrower - e.g. a <12 x i8> being formed by a shuffle
with two <8 x i8> inputs - we would lower the shuffle to a sequence of extracts
and inserts.

Instead, we can form a larger vector_shuffle, and then extract a subvector
of the right size - e.g. shuffle the two <8 x i8> inputs into a <16 x i8>
and then extract a <12 x i8>.

This also includes a target-specific X86 combine that in the presence of
AVX2 combines:
(vector_shuffle <mask> (concat_vectors t1, undef)
(concat_vectors t2, undef))
into:
(vector_shuffle <mask> (concat_vectors t1, t2), undef)
in cases where this allows us to form VPERMD/VPERMQ.

(This is not a separate commit, as that pattern does not appear without
the DAGBuilder change.)

llvm-svn: 280418

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# 5081ac27 01-Sep-2016 Hal Finkel <hfinkel@anl.gov>

Add ISD::EH_DWARF_CFA, simplify @llvm.eh.dwarf.cfa on Mips, fix on PowerPC

LLVM has an @llvm.eh.dwarf.cfa intrinsic, used to lower the GCC-compatible
__builtin_dwarf_cfa() builtin. As pointed out in

Add ISD::EH_DWARF_CFA, simplify @llvm.eh.dwarf.cfa on Mips, fix on PowerPC

LLVM has an @llvm.eh.dwarf.cfa intrinsic, used to lower the GCC-compatible
__builtin_dwarf_cfa() builtin. As pointed out in PR26761, this is currently
broken on PowerPC (and likely on ARM as well). Currently, @llvm.eh.dwarf.cfa is
lowered using:

ADD(FRAMEADDR, FRAME_TO_ARGS_OFFSET)

where FRAME_TO_ARGS_OFFSET defaults to the constant zero. On x86,
FRAME_TO_ARGS_OFFSET is lowered to 2*SlotSize. This setup, however, does not
work for PowerPC. Because of the way that the stack layout works, the canonical
frame address is not exactly (FRAMEADDR + FRAME_TO_ARGS_OFFSET) on PowerPC
(there is a lower save-area offset as well), so it is not just a matter of
implementing FRAME_TO_ARGS_OFFSET for PowerPC (unless we redefine its
semantics -- We can do that, since it is currently used only for
@llvm.eh.dwarf.cfa lowering, but the better to directly lower the CFA construct
itself (since it can be easily represented as a fixed-offset FrameIndex)). Mips
currently does this, but by using a custom lowering for ADD that specifically
recognizes the (FRAMEADDR, FRAME_TO_ARGS_OFFSET) pattern.

This change introduces a ISD::EH_DWARF_CFA node, which by default expands using
the existing logic, but can be directly lowered by the target. Mips is updated
to use this method (which simplifies its implementation, and I suspect makes it
more robust), and updates PowerPC to do the same.

Fixes PR26761.

Differential Revision: https://reviews.llvm.org/D24038

llvm-svn: 280350

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# 260daed1 25-Aug-2016 Michael Kuperstein <mkuper@google.com>

Reuse an SDLoc throughout a function. NFC.

llvm-svn: 279767


# cd1d5aaf 17-Aug-2016 Justin Bogner <mail@justinbogner.com>

Replace a few more "fall through" comments with LLVM_FALLTHROUGH

Follow up to r278902. I had missed "fall through", with a space.

llvm-svn: 278970


# 71b43c5c 17-Aug-2016 Ayman Musa <ayman.musa@intel.com>

Fix bug in DAGBuilder for getelementptr with expanded vector.

Replacing the usage of MVT with EVT in case the vector type is expanded.
Differential Revision: https://reviews.llvm.org/D23306

llvm-sv

Fix bug in DAGBuilder for getelementptr with expanded vector.

Replacing the usage of MVT with EVT in case the vector type is expanded.
Differential Revision: https://reviews.llvm.org/D23306

llvm-svn: 278913

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# c96f421a 17-Aug-2016 Ayman Musa <ayman.musa@intel.com>

First commit (test commit) - Adding empty line.

llvm-svn: 278910


# dfad9b20 15-Aug-2016 Wolfgang Pieb <Wolfgang.Pieb@sony.com>

Local variables whose address is taken and passed on to a call are described
in debug info using their stack slots instead of as an indirection of param reg + 0
offset. This is done by detecting Fra

Local variables whose address is taken and passed on to a call are described
in debug info using their stack slots instead of as an indirection of param reg + 0
offset. This is done by detecting FrameIndexSDNodes in SelectionDAG and generating
FrameIndexDbgValues for them. This ultimately generates DBG_VALUEs with stack
location operands.

Differential Revision: http://reviews.llvm.org/D23283

llvm-svn: 278703

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# 0a16c228 11-Aug-2016 David Majnemer <david.majnemer@gmail.com>

Use range algorithms instead of unpacking begin/end

No functionality change is intended.

llvm-svn: 278417


# 4dd6c249 08-Aug-2016 Diana Picus <diana.picus@linaro.org>

[SelectionDAG] Refactor visitInlineAsm a bit. NFCI.

This shaves off ~100 lines from visitInlineAsm.

llvm-svn: 277987


# b99d1cc7 29-Jul-2016 Andrew Kaylor <andrew.kaylor@intel.com>

Recommitting r275284: add support to inline __builtin_mempcpy

Patch by Sunita Marathe

Third try, now following fixes to MSan to handle mempcy in such a way that this commit won't break the MSan bui

Recommitting r275284: add support to inline __builtin_mempcpy

Patch by Sunita Marathe

Third try, now following fixes to MSan to handle mempcy in such a way that this commit won't break the MSan buildbots. (Thanks, Evegenii!)

llvm-svn: 277189

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# 941a705b 28-Jul-2016 Matthias Braun <matze@braunis.de>

MachineFunction: Return reference for getFrameInfo(); NFC

getFrameInfo() never returns nullptr so we should use a reference
instead of a pointer.

llvm-svn: 277017


# f990fa5f 27-Jul-2016 Andrew Kaylor <andrew.kaylor@intel.com>

Reverting r276771 due to MSan failures.

llvm-svn: 276824


# 3104a6ba 26-Jul-2016 Andrew Kaylor <andrew.kaylor@intel.com>

Re-committing r275284: add support to inline __builtin_mempcpy

Patch by Sunita Marathe

Differential Revision: http://reviews.llvm.org/D21920

llvm-svn: 276771


# 9c375817 15-Jul-2016 Justin Lebar <jlebar@google.com>

[SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore, and friends.

Summary:
Instead, we take a single flags arg (a bitset).

Also add a default 0 alignment, and change the or

[SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore, and friends.

Summary:
Instead, we take a single flags arg (a bitset).

Also add a default 0 alignment, and change the order of arguments so the
alignment comes before the flags.

This greatly simplifies many callsites, and fixes a bug in
AMDGPUISelLowering, wherein the order of the args to getLoad was
inverted. It also greatly simplifies the process of adding another flag
to getLoad.

Reviewers: chandlerc, tstellarAMD

Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits

Differential Revision: http://reviews.llvm.org/D22249

llvm-svn: 275592

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# 0af80cd6 15-Jul-2016 Justin Lebar <jlebar@google.com>

[CodeGen] Take a MachineMemOperand::Flags in MachineFunction::getMachineMemOperand.

Summary:
Previously we took an unsigned.

Hooray for type-safety.

Reviewers: chandlerc

Subscribers: dsanders, ll

[CodeGen] Take a MachineMemOperand::Flags in MachineFunction::getMachineMemOperand.

Summary:
Previously we took an unsigned.

Hooray for type-safety.

Reviewers: chandlerc

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D22282

llvm-svn: 275591

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# 4d36e770 13-Jul-2016 Michael Kuperstein <mkuper@google.com>

Fix copy/paste bug in r275340.

llvm-svn: 275343


# be837fa4 13-Jul-2016 Michael Kuperstein <mkuper@google.com>

[DAG] Correctly chain masked loads

If a masked loads is not added to the chain, it should not reset the chain's
root.

This fixes the remaining part of PR28515.

llvm-svn: 275340


# 346dd7f1 13-Jul-2016 Andrew Kaylor <andrew.kaylor@intel.com>

Reverting r275284 due to platform-specific test failures

llvm-svn: 275304


# 12cccdd7 13-Jul-2016 Andrew Kaylor <andrew.kaylor@intel.com>

Fix for Bug 26903, adds support to inline __builtin_mempcpy

Patch by Sunita Marathe

Differential Revision: http://reviews.llvm.org/D21920

llvm-svn: 275284


# 4d09892e 10-Jul-2016 Benjamin Kramer <benny.kra@googlemail.com>

Give helper classes/functions internal linkage. NFC.

llvm-svn: 275014


# 1b824c9e 08-Jul-2016 Duncan P. N. Exon Smith <dexonsmith@apple.com>

SelectionDAG: Avoid implicit iterator conversions in SelectionDAGBuilder, NFC

llvm-svn: 274907


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