History log of /llvm-project/llvm/lib/CodeGen/PostRASchedulerList.cpp (Results 76 – 100 of 227)
Revision (<<< Hide revision tags) (Show revision tags >>>) Date Author Comments
# f1ff84c6 12-Nov-2012 Andrew Trick <atrick@apple.com>

misched: Infrastructure for weak DAG edges.

This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edg

misched: Infrastructure for weak DAG edges.

This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edges.

llvm-svn: 167738

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# c30a9af2 15-Oct-2012 Jakob Stoklund Olesen <stoklund@2pi.dk>

Switch most getReservedRegs() clients to the MRI equivalent.

Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.

llvm-svn: 165983


# 19f49ac6 11-Sep-2012 Manman Ren <mren@apple.com>

Release build: guard dump functions with
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"

No functional change. Update r163339.

llvm-svn: 163653


# 742534c4 06-Sep-2012 Manman Ren <mren@apple.com>

Release build: guard dump functions with "ifndef NDEBUG"

No functional change.

llvm-svn: 163339


# a538d831 22-Aug-2012 Craig Topper <craig.topper@gmail.com>

Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.

llvm-svn: 162347


# 05ff4667 06-Jun-2012 Andrew Trick <atrick@apple.com>

Move RegisterClassInfo.h.

Allow targets to access this API. It's required for RegisterPressure.

llvm-svn: 158102


# 628a39fa 06-Jun-2012 Benjamin Kramer <benny.kra@googlemail.com>

Remove unused private fields found by clang's new -Wunused-private-field.

There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too

Remove unused private fields found by clang's new -Wunused-private-field.

There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.

llvm-svn: 158090

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# 54038d79 01-Jun-2012 Jakob Stoklund Olesen <stoklund@2pi.dk>

Switch all register list clients to the new MC*Iterator interface.

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in

Switch all register list clients to the new MC*Iterator interface.

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854

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Revision tags: llvmorg-3.1.0, llvmorg-3.1.0-rc3, llvmorg-3.1.0-rc2
# 9a091475 23-Apr-2012 Preston Gurd <preston.gurd@intel.com>

This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks whi

This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.

This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.

This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.

The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().

It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.

It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.

Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.

Patch by Andy Zhang!

Thanks to Jakob and Anton for their reviews.

llvm-svn: 155395

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Revision tags: llvmorg-3.1.0-rc1
# 8c207e47 09-Mar-2012 Andrew Trick <atrick@apple.com>

misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private.

llvm-svn: 152382


# 9a0c5839 07-Mar-2012 Andrew Trick <atrick@apple.com>

misched prep: Expose the ScheduleDAGInstrs interface so targets may
implement their own MachineScheduler.

llvm-svn: 152261


# a316faab 07-Mar-2012 Andrew Trick <atrick@apple.com>

misched prep: rename InsertPos to End.

ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.

llvm-svn: 152256


# 52226d40 07-Mar-2012 Andrew Trick <atrick@apple.com>

misched preparation: rename core scheduler methods for consistency.

We had half the API with one convention, half with another. Now was a
good time to clean it up.

llvm-svn: 152255


# 60cf03e7 07-Mar-2012 Andrew Trick <atrick@apple.com>

misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.

ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.

ScheduleDAGInstrs e

misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.

ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.

ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.

ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.

Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.

- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.

- Added ScheduleDAGInstrs::begin()/end() public API.

- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.

llvm-svn: 152208

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# e932bb77 07-Mar-2012 Andrew Trick <atrick@apple.com>

misched preparation: modularize schedule emission.

ScheduleDAG has nothing to do with how the instructions are scheduled.

llvm-svn: 152206


# edee68ce 07-Mar-2012 Andrew Trick <atrick@apple.com>

misched preparation: modularize schedule printing.

ScheduleDAG will not refer to the scheduled instruction sequence.

llvm-svn: 152205


# 46a58664 07-Mar-2012 Andrew Trick <atrick@apple.com>

misched preparation: modularize schedule verification.

ScheduleDAG will not refer to the scheduled instruction sequence.

llvm-svn: 152204


# 4b02a29e 05-Mar-2012 Craig Topper <craig.topper@gmail.com>

Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.

llvm-svn: 152016


# ef8bf395 23-Feb-2012 Benjamin Kramer <benny.kra@googlemail.com>

BitVectorize loop.

llvm-svn: 151274


# 796fd469 23-Feb-2012 Benjamin Kramer <benny.kra@googlemail.com>

post-ra-sched: Turn the KillIndices vector into a bitvector, it only stored two meaningful states.

Rename it to LiveRegs to make it more clear what's stored inside.

llvm-svn: 151273


# 21974b1f 23-Feb-2012 Benjamin Kramer <benny.kra@googlemail.com>

post-ra-sched: Replace a std::set of regs with a bitvector.

Assuming that a single std::set node adds 3 control words, a bitvector
can store (3*8+4)*8=224 registers in the allocated memory of a sing

post-ra-sched: Replace a std::set of regs with a bitvector.

Assuming that a single std::set node adds 3 control words, a bitvector
can store (3*8+4)*8=224 registers in the allocated memory of a single
element in the std::set (x86_64). Also we don't have to call malloc
for every register added.

llvm-svn: 151269

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# a793a59f 23-Feb-2012 Jakob Stoklund Olesen <stoklund@2pi.dk>

Make calls scheduling boundaries post-ra.

Before register allocation, instructions can be moved across calls in
order to reduce register pressure. After register allocation, we don't
gain a lot by

Make calls scheduling boundaries post-ra.

Before register allocation, instructions can be moved across calls in
order to reduce register pressure. After register allocation, we don't
gain a lot by moving callee-saved defs across calls. In fact, since the
scheduler doesn't have a good idea how registers are used in the callee,
it can't really make good scheduling decisions.

This changes the schedule in two ways: 1. Latencies to call uses and
defs are no longer accounted for, causing some random shuffling around
calls. This isn't really a problem since those uses and defs are
inaccurate proxies for what happens inside the callee. They don't
represent registers used by the call instruction itself.

2. Instructions are no longer moved across calls. This didn't happen
very often, and the scheduling decision was made on dubious information
anyway.

As with any scheduling change, benchmark numbers shift around a bit,
but there is no positive or negative trend from this change.

This makes the post-ra scheduler 5% faster for ARM targets.

The secret motivation for this patch is the introduction of register
mask operands representing call clobbers. The most efficient way of
handling regmasks in ScheduleDAGInstrs is to model them as barriers for
physreg live ranges, but not for virtreg live ranges. That's fine
pre-ra, but post-ra it would have the same effect as this patch.

llvm-svn: 151265

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# 28d4803a 23-Feb-2012 Jakob Stoklund Olesen <stoklund@2pi.dk>

Handle regmasks in FixupKills.

llvm-svn: 151226


# 760b134f 22-Feb-2012 Craig Topper <craig.topper@gmail.com>

Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.

llvm-svn: 151134


# 1fa5bcbe 08-Feb-2012 Andrew Trick <atrick@apple.com>

Codegen pass definition cleanup. No functionality.

Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.

Codegen pass definition cleanup. No functionality.

Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

llvm-svn: 150100

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