Fix warning; NFC

llvm-svn: 283851

MIRParser: generic register operands with types

This should fix the fallout of r283848.

llvm-svn: 283850

MIRParser: Rewrite register info initialization; mostly NFC

This changes MachineRegisterInfo to be initializes after parsing all
instructions. This is in preparation for upcoming commits that allow

MIRParser: Rewrite register info initialization; mostly NFC

This changes MachineRegisterInfo to be initializes after parsing all
instructions. This is in preparation for upcoming commits that allow the
register class specification on the operand or deduce them from the
MCInstrDesc.

This commit removes the unused feature of having nonsequential register
numbers. This was confusing anyway as the vreg numbers would be
different after parsing when you had "holes" in your numbering.

This patch also introduces the concept of an incomplete virtual
register. An incomplete virtual register may be used during .mir parsing
to construct MachineOperands without knowing the exact register class
(or register bank) yet.

NFC except for some error messages.

Differential Revision: https://reviews.llvm.org/D22397

llvm-svn: 283848

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[TargetRegisterInfo, AArch64] Add target hook for isConstantPhysReg().

Summary:
The current implementation of isConstantPhysReg() checks for defs of
physical registers to determine if they are const

[TargetRegisterInfo, AArch64] Add target hook for isConstantPhysReg().

Summary:
The current implementation of isConstantPhysReg() checks for defs of
physical registers to determine if they are constant. Some
architectures (e.g. AArch64 XZR/WZR) have registers that are constant
and may be used as destinations to indicate the generated value is
discarded, preventing isConstantPhysReg() from returning true. This
change adds a TargetRegisterInfo hook that overrides the no defs check
for cases such as this.

Reviewers: MatzeB, qcolombet, t.p.northover, jmolloy

Subscribers: junbuml, aemerson, mcrosier, rengolin

Differential Revision: https://reviews.llvm.org/D24570

llvm-svn: 282543

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GlobalISel: remove "unsized" LLT

It was only really there as a sentinel when instructions had to have precisely
one type. Now that registers are typed, each register really has to have a type
that i

GlobalISel: remove "unsized" LLT

It was only really there as a sentinel when instructions had to have precisely
one type. Now that registers are typed, each register really has to have a type
that is sized.

llvm-svn: 281599

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GlobalISel: disambiguate types when printing MIR

Some generic instructions have multiple types. While in theory these always be
discovered by inspecting the single definition of each generic vreg, i

GlobalISel: disambiguate types when printing MIR

Some generic instructions have multiple types. While in theory these always be
discovered by inspecting the single definition of each generic vreg, in
practice those definitions won't always be local and traipsing through a big
function to find them will not be fun.

So this changes MIRPrinter to print out the type of uses as well as defs, if
they're known to be different or not known to be the same.

On the parsing side, we're a little more flexible: provided each register is
given a type in at least one place it's mentioned (and all types are
consistent) we accept the MIR. This doesn't introduce ambiguity but makes
writing tests manually a bit less painful.

llvm-svn: 281204

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GlobalISel: move type information to MachineRegisterInfo.

We want each register to have a canonical type, which means the best place to
store this is in MachineRegisterInfo rather than on every Mach

GlobalISel: move type information to MachineRegisterInfo.

We want each register to have a canonical type, which means the best place to
store this is in MachineRegisterInfo rather than on every MachineInstr that
happens to use or define that register.

Most changes following from this are pretty simple (you need an MRI anyway if
you're going to be doing any transformations, so just check the type there).
But legalization doesn't really want to check redundant operands (when, for
example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's
operand type field to encode these constraints and limit legalization's work.

As an added bonus, more validation is possible, both in MachineVerifier and
MachineIRBuilder (coming soon).

llvm-svn: 281035

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MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it

tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there
is not need to change it or save/parse

MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it

tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there
is not need to change it or save/parse it in a .mir file.
Make the field const and move the initialization LiveIntervalAnalysis to the
MachineRegisterInfo constructor. Also cleanup some code and fix some
instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead
of TargetSubtargetInfo::enableSubRegLiveness().

llvm-svn: 279676

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[GlobalISel] Introduce an instruction selector.

And implement it for AArch64, supporting x/w ADD/OR.

Differential Revision: https://reviews.llvm.org/D22373

llvm-svn: 276875

[GlobalISel] Mark newly-created gvregs as having a bank.

Also verify that we never try to set the size of a vreg associated
to a register class.

Report an error when we encounter that in MIR. Fix a

[GlobalISel] Mark newly-created gvregs as having a bank.

Also verify that we never try to set the size of a vreg associated
to a register class.

Report an error when we encounter that in MIR. Fix a testcase that
hit that error and had a size for no reason.

llvm-svn: 276012

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[IPRA] Properly compute register usage at call sites.

Differential Revision: http://reviews.llvm.org/D21395
Patch by Vivek Pandya.
PR28144

llvm-svn: 275087

Replace MachineRegisterInfo::TracksLiveness with a MachineFunctionProperty

Use the MachineFunctionProperty mechanism to indicate whether the
liveness info is accurate instead of a bool flag on MRI.

Replace MachineRegisterInfo::TracksLiveness with a MachineFunctionProperty

Use the MachineFunctionProperty mechanism to indicate whether the
liveness info is accurate instead of a bool flag on MRI.
Keeps the MRI accessor function for convenience. NFC

Differential Revision: http://reviews.llvm.org/D18767

llvm-svn: 266020

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[MachineRegisterInfo] Track register bank for virtual registers.
A virtual register may have either a register bank or a register class.
This is represented by a PointerUnion between the related clas

[MachineRegisterInfo] Track register bank for virtual registers.
A virtual register may have either a register bank or a register class.
This is represented by a PointerUnion between the related classes.

Typically, a virtual register went through the following states
regarding register class and register bank:

1. Creation: None is set. Virtual registers are fully generic.
2. Register bank assignment: Register bank is set. Virtual registers
live into a register bank, but we do not know the constraints they need
to fulfil.
3. Instruction selection: Register class is set. Virtual registers are
bound by encoding constraints.

To map these states to GlobalISel, the IRTranslator implements #1,
RegBankSelect #2, and Select #3.

llvm-svn: 265696

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Replace MachineRegisterInfo::isSSA() with a MachineFunctionProperty

Use the MachineFunctionProperty mechanism to indicate whether a MachineFunction
is in SSA form instead of a custom method on Machi

Replace MachineRegisterInfo::isSSA() with a MachineFunctionProperty

Use the MachineFunctionProperty mechanism to indicate whether a MachineFunction
is in SSA form instead of a custom method on MachineRegisterInfo. NFC

Differential Revision: http://reviews.llvm.org/D18574

llvm-svn: 265318

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[MachineRegisterInfo] Add a method to set the size of a virtual register a posteriori.
This is required for mir testing.

llvm-svn: 262861

[MachineRegisterInfo] Get rid of the global-isel ifdefs.
One additional pointer is not a big deal size-wise and it makes
the code much nicer!

llvm-svn: 262856

[GlobalISel][MachineRegisterInfo] Add a method to create generic vregs.
For now, generic virtual registers will not have a register class. We may want
to change that. For instance, if we want to use

[GlobalISel][MachineRegisterInfo] Add a method to create generic vregs.
For now, generic virtual registers will not have a register class. We may want
to change that. For instance, if we want to use all the methods from
TargetRegisterInfo with generic virtual registers, we need to either have some
sort of generic register classes that do what we want, or teach those methods
how to deal with nullptr register class.

Although the latter seems easy enough to do, we may still want to differenciate
generic register classes from nullptr to catch cases where nullptr gets
introduced by a bug of some sort.

Anyway, I will file a PR to keep track of that.

llvm-svn: 260474

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[GlobalISel] Remember the size of generic virtual registers

llvm-svn: 260468

Scheduler / Regalloc: use unique_ptr[] instead of std::vector

vector.resize() is significantly slower than memset in many STLs
and the cost of initializing these vectors is significant on targets
wi

Scheduler / Regalloc: use unique_ptr[] instead of std::vector

vector.resize() is significantly slower than memset in many STLs
and the cost of initializing these vectors is significant on targets
with many registers. Since we don't need the overhead of a vector,
use a simple unique_ptr instead.

llvm-svn: 254526

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Refactor: Simplify boolean conditional return statements in lib/CodeGen.

Patch by Richard.

llvm-svn: 251213

TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC

llvm-svn: 248623

MachineRegisterInfo: Introduce isPhysRegUsed()

This method checks whether a physical regiser or any of its aliases are
used in the function.

Using this function in SIRegisterInfo::findUnusedReg() s

MachineRegisterInfo: Introduce isPhysRegUsed()

This method checks whether a physical regiser or any of its aliases are
used in the function.

Using this function in SIRegisterInfo::findUnusedReg() should also fix
this reported failure:

http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20150803/292143.html
http://reviews.llvm.org/rL242173#inline-533

The report doesn't come with a testcase and I don't know enough about
AMDGPU to create one myself.

llvm-svn: 245329

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Reset the virtual registers in liveins when clearing the virtual registers.

This commit zeroes out the virtual register references in the machine
function's liveins in the class 'MachineRegisterInfo

Reset the virtual registers in liveins when clearing the virtual registers.

This commit zeroes out the virtual register references in the machine
function's liveins in the class 'MachineRegisterInfo' when the virtual
register definitions are cleared.

Reviewers: Matthias Braun
llvm-svn: 243290

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MachineRegisterInfo: Remove UsedPhysReg infrastructure

We have a detailed def/use lists for every physical register in
MachineRegisterInfo anyway, so there is little use in maintaining an
additional

MachineRegisterInfo: Remove UsedPhysReg infrastructure

We have a detailed def/use lists for every physical register in
MachineRegisterInfo anyway, so there is little use in maintaining an
additional bitset of which ones are used.

Removing it frees us from extra book keeping. This simplifies
VirtRegMap.

Differential Revision: http://reviews.llvm.org/D10911

llvm-svn: 242173

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PrologEpilogInserter: Rewrite API to determine callee save regsiters.

This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan():

- Rename the function to determineCalleeSaves()
- Pas

PrologEpilogInserter: Rewrite API to determine callee save regsiters.

This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan():

- Rename the function to determineCalleeSaves()
- Pass a bitset of callee saved registers by reference, thus avoiding
the function-global PhysRegUsed bitset in MachineRegisterInfo.
- Without PhysRegUsed the implementation is fine tuned to not save
physcial registers which are only read but never modified.

Related to rdar://21539507

Differential Revision: http://reviews.llvm.org/D10909

llvm-svn: 242165

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