Simplify a few more uses of reg_iterator.

llvm-svn: 82812

Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
-

Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381

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Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.

llvm-svn: 73346

Move MachineRegisterInfo::setRegClass out of line.

llvm-svn: 69126

Move createVirtualRegister out-of-line.

llvm-svn: 60684

Add a register class -> virtual registers map.

llvm-svn: 57844

Assert that all MachineInstrs update PhysRegUseDefLists in
their cleanup code.

llvm-svn: 53194

Added debugging routine dumpUses.

llvm-svn: 47042

Rename MRegisterInfo to TargetRegisterInfo.

llvm-svn: 46930

switch the register iterator to act more like hte LLVM value iterator: dereferencing
it now returns the machineinstr of the use. To get the operand, use I.getOperand().

Add a new MachineRegisterInf

switch the register iterator to act more like hte LLVM value iterator: dereferencing
it now returns the machineinstr of the use. To get the operand, use I.getOperand().

Add a new MachineRegisterInfo::replaceRegWith, which is basically like
Value::replaceAllUsesWith.

llvm-svn: 45482

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Add a trivial but handy function to efficiently return the machine
instruction that defines the specified vreg. Crazy.

llvm-svn: 45480

Implement automatically updated def/use lists for all MachineInstr register
operands. The lists are currently kept in MachineRegisterInfo, but it does
not yet provide an iterator interface to them.

Implement automatically updated def/use lists for all MachineInstr register
operands. The lists are currently kept in MachineRegisterInfo, but it does
not yet provide an iterator interface to them.

llvm-svn: 45477

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Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
m

Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467

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