Move CalculateRegClass to MRI::recomputeRegClass.

This function doesn't have anything to do with spill weights, and MRI
already has functions for manipulating the register class of a virtual
registe

Move CalculateRegClass to MRI::recomputeRegClass.

This function doesn't have anything to do with spill weights, and MRI
already has functions for manipulating the register class of a virtual
register.

llvm-svn: 137123

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Add an isSSA() flag to MachineRegisterInfo.

This flag is true from isel to register allocation when the machine
function is required to be in SSA form. The TwoAddressInstructionPass
and PHIEliminat

Add an isSSA() flag to MachineRegisterInfo.

This flag is true from isel to register allocation when the machine
function is required to be in SSA form. The TwoAddressInstructionPass
and PHIElimination passes clear the flag.

The SSA flag wil be used by the machine code verifier to check for SSA
form, and eventually an assertion can enforce it in +Asserts builds.
This will catch the common target error of creating machine code with
multiple defs of a virtual register.

llvm-svn: 136532

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Remove RegClass2VRegMap from MachineRegisterInfo.

llvm-svn: 133967

Make it possible to have unallocatable register classes.

Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
r

Make it possible to have unallocatable register classes.

Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508

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Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table e

Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working.
- The debugger needs to be aware of prolog_end attribute attached with line table entries.
- The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)

llvm-svn: 126155

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Keep track of incoming argument's location while emitting LiveIns.

llvm-svn: 124611

Use IndexedMap for MachineRegisterInfo as well. No functional change.

llvm-svn: 123106

Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.

This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA

Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.

This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.

llvm-svn: 115875

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Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.

llvm-svn: 108062

Teach EmitLiveInCopies to omit copies for unused virtual registers,
and to clean up unused incoming physregs from the live-in list.

llvm-svn: 106805

Don't leak RegClass2VRegMap, which is now a new[] array instead of a
std::vector.

llvm-svn: 106298

Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

llvm-svn: 106296

Remove unused function.

llvm-svn: 105100

Remove schedule-livein-copies. It's not being used.

llvm-svn: 105095

Avoid adding duplicate function live-in's.

llvm-svn: 104560

Add a utility function for conservatively clearing kill flags, and make
use of it in MachineCSE.

llvm-svn: 103726

Silence warning

llvm-svn: 103508

Simplify the tracking of used physregs to a bulk bitor followed by a transitive
closure after allocating all blocks.

Add a few more test cases for -regalloc=fast.

llvm-svn: 103500

Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.

llvm-svn: 103194

Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done.

llvm-svn: 102554

Insert dbg_value instructions for function entry block liveins (i.e. function arguments).

llvm-svn: 102368

Move the code for initialing the entry block livein set out of
SelectionDAGISel.

llvm-svn: 101258

Move the code for emitting livein copies out of SelectionDAGISel.

llvm-svn: 101254

Move MachineRegisterInfo's isLiveIn and isLiveOut out of line.

llvm-svn: 101145

Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.

llvm-svn: 97663