Add MachineRegisterInfo::moveOperands().

This function works like memmove() for MachineOperands, except it also
updates any use-def chains containing the moved operands.

The use-def chains are upda

Add MachineRegisterInfo::moveOperands().

This function works like memmove() for MachineOperands, except it also
updates any use-def chains containing the moved operands.

The use-def chains are updated without affecting the order of operands
in the list. That isn't possible when using the
removeRegOperandFromUseList() and addRegOperandToUseList() functions.

Callers to follow soon.

llvm-svn: 171597

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Revert r168630, r168631, and r168633 as these are causing nightly test failures.

llvm-svn: 168751

Add an assertion to ensure freezeReservedRegs() is only ever called once.

llvm-svn: 168633

Switch MRI::UsedPhysRegs to a register unit bit vector.

This is a more compact, less redundant representation, and it avoids
scanning long lists of aliases for ARM D-registers, for example.

llvm-sv

Switch MRI::UsedPhysRegs to a register unit bit vector.

This is a more compact, less redundant representation, and it avoids
scanning long lists of aliases for ARM D-registers, for example.

llvm-svn: 166124

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Freeze the reserved registers as soon as isel is complete.

Also provide an MRI::getReservedRegs() function to access the frozen
register set, and isReserved() and isAllocatable() methods to test
ind

Freeze the reserved registers as soon as isel is complete.

Also provide an MRI::getReservedRegs() function to access the frozen
register set, and isReserved() and isAllocatable() methods to test
individual registers.

The various implementations of TRI::getReservedRegs() are quite
complicated, and many passes need to look at the reserved register set.
This patch makes it possible for these passes to use the cached copy in
MRI, avoiding a lot of malloc traffic and repeated calculations.

llvm-svn: 165982

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Reapply r161633-161634 "Partition use lists so defs always come before uses.""

No changes to these patches, MRI needed to be notified when changing
uses into defs and vice versa.

llvm-svn: 161644

Revert r161633-161634 "Partition use lists so defs always come before uses."

These commits broke a number of buildbots.

llvm-svn: 161640

Partition use lists so defs always come before uses.

This makes it possible to speed up def_iterator by stopping at the first
use. This makes def_empty() and getUniqueVRegDef() much faster when
ther

Partition use lists so defs always come before uses.

This makes it possible to speed up def_iterator by stopping at the first
use. This makes def_empty() and getUniqueVRegDef() much faster when
there are many uses.

In a +Asserts build, LiveVariables is 100x faster in one case because
getVRegDef() has an assertion that would scan to the end of a
def_iterator chain.

Spill weight calculation is significantly faster (300x in one case)
because isTriviallyReMaterializable() calls MRI->isConstantPhysReg(%RIP)
which calls def_empty(%RIP).

llvm-svn: 161634

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Don't use pointer-pointers for the register use lists.

Use a more conventional doubly linked list where the Prev pointers form
a cycle. This means it is no longer necessary to adjust the Prev
pointe

Don't use pointer-pointers for the register use lists.

Use a more conventional doubly linked list where the Prev pointers form
a cycle. This means it is no longer necessary to adjust the Prev
pointers when reallocating the VRegInfo array.

The test changes are required because the register allocation hint is
using the use-list order to break ties.

llvm-svn: 161633

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Move use list management into MachineRegisterInfo.

Register MachineOperands are kept in linked lists accessible via MRI's
reg_iterator interfaces. The linked list management was handled partly
by Ma

Move use list management into MachineRegisterInfo.

Register MachineOperands are kept in linked lists accessible via MRI's
reg_iterator interfaces. The linked list management was handled partly
by MachineOperand methods, partly by MRI methods.

Move all of the list management into MRI, delete
MO::AddRegOperandToRegInfo() and MO::RemoveRegOperandFromRegInfo().

Be more explicit about handling the cases where an MRI pointer isn't
available.

llvm-svn: 161632

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Inline MachineRegisterInfo::hasOneUse

llvm-svn: 161007

Added assertion in getVRegDef of MachineRegisterInfo to make sure the virtual
register does not have multiple definitions. Modified TwoAddressInstructionPass
to use getUniqueVRegDef instead of getVRe

Added assertion in getVRegDef of MachineRegisterInfo to make sure the virtual
register does not have multiple definitions. Modified TwoAddressInstructionPass
to use getUniqueVRegDef instead of getVRegDef.

llvm-svn: 159545

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Add getUniqueVRegDef to MachineRegisterInfo.
This comes in handy during peephole optimization.

llvm-svn: 159453

Switch all register list clients to the new MC*Iterator interface.

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in

Switch all register list clients to the new MC*Iterator interface.

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854

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Add an MRI::tracksLiveness() flag.

Late optimization passes like branch folding and tail duplication can
transform the machine code in a way that makes it expensive to keep the
register liveness inf

Add an MRI::tracksLiveness() flag.

Late optimization passes like branch folding and tail duplication can
transform the machine code in a way that makes it expensive to keep the
register liveness information up to date. There is a fuzzy line between
register allocation and late scheduling where the liveness information
degrades.

The MRI::tracksLiveness() flag makes the line clear: While true,
liveness information is accurate, and can be used for register
scavenging. Once the flag is false, liveness information is not
accurate, and can only be used as a hint.

Late passes generally don't need the liveness information, but they will
sometimes use the register scavenger to help update it. The scavenger
enforces strict correctness, and we have to spend a lot of code to
update register liveness that may never be used.

llvm-svn: 153511

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Microoptimize getVRegDef. def_begin isn't free, don't compute it twice.

llvm-svn: 152492

Use uint16_t to store register overlaps to reduce static data.

llvm-svn: 152001

Clear virtual registers after they are no longer referenced.

Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0.
This makes sharing code for pre/postRA passes more robust.
No

Clear virtual registers after they are no longer referenced.

Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0.
This makes sharing code for pre/postRA passes more robust.
Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA().
To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs().

PEI resets virtual regs when it's done scavenging.

PTX will either have to provide its own PEI pass or assign physregs.

llvm-svn: 151032

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Transfer regmasks to MRI.

MRI keeps track of which physregs have been used. Make sure it gets
updated with all the regmask-clobbered registers.

Delete the closePhysRegsUsed() function which isn't n

Transfer regmasks to MRI.

MRI keeps track of which physregs have been used. Make sure it gets
updated with all the regmask-clobbered registers.

Delete the closePhysRegsUsed() function which isn't necessary.

llvm-svn: 150830

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Extract method for detecting constant unallocatable physregs.

It is safe to move uses of such registers.

llvm-svn: 148259

Freeze reserved registers before starting register allocation.

The register allocators don't currently support adding reserved
registers while they are running. Extend the MRI API to keep track of

Freeze reserved registers before starting register allocation.

The register allocators don't currently support adding reserved
registers while they are running. Extend the MRI API to keep track of
the set of reserved registers when register allocation started.

Target hooks like hasFP() and needsStackRealignment() can look at this
set to avoid reserving more registers during register allocation.

llvm-svn: 147577

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Handle sub-register operands in recomputeRegClass().

Now that getMatchingSuperRegClass() returns accurate results, it can be
used to compute constraints imposed by instructions using a sub-register

Handle sub-register operands in recomputeRegClass().

Now that getMatchingSuperRegClass() returns accurate results, it can be
used to compute constraints imposed by instructions using a sub-register
of a virtual register.

This means we can recompute the register class of any virtual register
by combining the constraints from all its uses.

llvm-svn: 146874

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Also inflate register classes around inline asm.

Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by in

Also inflate register classes around inline asm.

Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.

This fixes PR11078.

llvm-svn: 141836

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Move getCommonSubClass() into TRI.

It will soon need the context.

llvm-svn: 140896

Add a MinNumRegs argument to MRI::constrainRegClass().

The function will refuse to use a register class with fewer registers
than MinNumRegs. This can be used by clients to avoid accidentally
incre

Add a MinNumRegs argument to MRI::constrainRegClass().

The function will refuse to use a register class with fewer registers
than MinNumRegs. This can be used by clients to avoid accidentally
increase register pressure too much.

The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.

llvm-svn: 140339

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