Revision tags: llvmorg-15.0.0 |
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9aca7b02 |
| 29-Aug-2022 |
David Penry <david.penry@arm.com> |
[ModuloScheduler] Fix missing LLVM_DEBUG
Guard a debug message with LLVM_DEBUG
Differential Revision: https://reviews.llvm.org/D132895
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Revision tags: llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init |
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ced705c4 |
| 30-Jun-2022 |
David Penry <david.penry@arm.com> |
[ModuloSchedule] Add interface call to accept/reject SMS schedules
This interface allows a target to reject a proposed SMS schedule. For Hexagon/PowerPC, all schedules are accepted, leaving behavio
[ModuloSchedule] Add interface call to accept/reject SMS schedules
This interface allows a target to reject a proposed SMS schedule. For Hexagon/PowerPC, all schedules are accepted, leaving behavior unchanged. For ARM, schedules which exceed register pressure limits are rejected.
Also, two RegisterPressureTracker methods now need to be public so that register pressure can be computed by more callers.
Reapplication of D128941/(reversion:D132037) with small fix.
Differential Revision: https://reviews.llvm.org/D132170
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1c9f0408 |
| 17-Aug-2022 |
David Penry <david.penry@arm.com> |
Revert "[ModuloSchedule] Add interface call to accept/reject SMS schedules"
This reverts commit 8c4aea438c310816bb4e4f9a32d783381ef3182e.
Needed because buildbot failures (warnings) gave a clue tha
Revert "[ModuloSchedule] Add interface call to accept/reject SMS schedules"
This reverts commit 8c4aea438c310816bb4e4f9a32d783381ef3182e.
Needed because buildbot failures (warnings) gave a clue that there was a functional bug in the ARM rejection logic.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D132037
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8c4aea43 |
| 30-Jun-2022 |
David Penry <david.penry@arm.com> |
[ModuloSchedule] Add interface call to accept/reject SMS schedules
This interface allows a target to reject a proposed SMS schedule. For Hexagon/PowerPC, all schedules are accepted, leaving behavio
[ModuloSchedule] Add interface call to accept/reject SMS schedules
This interface allows a target to reject a proposed SMS schedule. For Hexagon/PowerPC, all schedules are accepted, leaving behavior unchanged. For ARM, schedules which exceed register pressure limits are rejected.
Also, two RegisterPressureTracker methods now need to be public so that register pressure can be computed by more callers.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D128941
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8d0383eb |
| 24-Jun-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
CodeGen: Remove AliasAnalysis from regalloc
This was stored in LiveIntervals, but not actually used for anything related to LiveIntervals. It was only used in one check for if a load instruction is
CodeGen: Remove AliasAnalysis from regalloc
This was stored in LiveIntervals, but not actually used for anything related to LiveIntervals. It was only used in one check for if a load instruction is rematerializable. I also don't think this was entirely correct, since it was implicitly assuming constant loads are also dereferenceable.
Remove this and rely only on the invariant+dereferenceable flags in the memory operand. Set the flag based on the AA query upfront. This should have the same net benefit, but has the possible disadvantage of making this AA query nonlazy.
Preserve the behavior of assuming pointsToConstantMemory implying dereferenceable for now, but maybe this should be changed.
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9e6d1f4b |
| 17-Jul-2022 |
Kazu Hirata <kazu@google.com> |
[CodeGen] Qualify auto variables in for loops (NFC)
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Revision tags: llvmorg-14.0.6 |
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4271a1ff |
| 18-Jun-2022 |
Kazu Hirata <kazu@google.com> |
[llvm] Call *set::insert without checking membership first (NFC)
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a98965d9 |
| 11-Jun-2022 |
Kazu Hirata <kazu@google.com> |
[CodeGen] Use llvm::erase_value (NFC)
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Revision tags: llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1 |
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907aedbb |
| 29-Mar-2022 |
David Penry <david.penry@arm.com> |
[NFC] Fix spelling/newlines in comments/debug messages
Just a few spelling mistakes and missing newlines
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D127162
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95a13425 |
| 05-Jun-2022 |
Fangrui Song <i@maskray.me> |
Remove unneeded cl::ZeroOrMore for cl::opt/cl::list options
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d86a206f |
| 05-Jun-2022 |
Fangrui Song <i@maskray.me> |
Remove unneeded cl::ZeroOrMore for cl::opt/cl::list options
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bcf4fa45 |
| 05-Jun-2022 |
Kazu Hirata <kazu@google.com> |
[CodeGen] Use a range-based for loop (NFC)
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36c7d79d |
| 04-Jun-2022 |
Fangrui Song <i@maskray.me> |
Remove unneeded cl::ZeroOrMore for cl::opt options
Similar to 557efc9a8b68628c2c944678c6471dac30ed9e8e. This commit handles options where cl::ZeroOrMore is more than one line below cl::opt.
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68dee839 |
| 05-Apr-2022 |
Thomas Preud'homme <thomasp@graphcore.ai> |
[MachinePipeliner] Fix unscheduled instruction
Prior to ordering instructions to be scheduled, the machine pipeliner update recurrence node sets in groupRemainingNodes() by adding in a given node se
[MachinePipeliner] Fix unscheduled instruction
Prior to ordering instructions to be scheduled, the machine pipeliner update recurrence node sets in groupRemainingNodes() by adding in a given node set any node on the dependency path from a node set with higher priority to the given node set. The function computePath() that determine what constitutes a path follows artificial dependencies.
However, when ordering the nodes in the resulting node sets, computeNodeOrder() calls ignoreDependence when looking at dependencies which ignores artificial dependencies. This can cause a node not to be scheduled which then causes wrong code generation and in the case of a debug build will lead to an assert failure in generatePhis() in ModuloScheduler.cpp.
This commit adds calls to ignoreDependence() in computePath() to not add any node in groupRemainingNodes() that would not be ordered by computeNodeOrder().
Reviewed By: sgundapa
Differential Revision: https://reviews.llvm.org/D124267
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dcb77643 |
| 29-Mar-2022 |
David Penry <david.penry@arm.com> |
Reapply [CodeGen][ARM] Enable Swing Module Scheduling for ARM
Fixed "private field is not used" warning when compiled with clang.
original commit: 28d09bbbc3d09c912b54a4d5edb32cab7de32a6f reverted
Reapply [CodeGen][ARM] Enable Swing Module Scheduling for ARM
Fixed "private field is not used" warning when compiled with clang.
original commit: 28d09bbbc3d09c912b54a4d5edb32cab7de32a6f reverted in: fa49021c68ef7a7adcdf7b8a44b9006506523191
------
This patch permits Swing Modulo Scheduling for ARM targets turns it on by default for the Cortex-M7. The t2Bcc instruction is recognized as a loop-ending branch.
MachinePipeliner is extended by adding support for "unpipelineable" instructions. These instructions are those which contribute to the loop exit test; in the SMS papers they are removed before creating the dependence graph and then inserted into the final schedule of the kernel and prologues. Support for these instructions was not previously necessary because current targets supporting SMS have only supported it for hardware loop branches, which have no loop-exit-contributing instructions in the loop body.
The current structure of the MachinePipeliner makes it difficult to remove/exclude these instructions from the dependence graph. Therefore, this patch leaves them in the graph, but adds a "normalization" method which moves them in the schedule to stage 0, which causes them to appear properly in kernel and prologues.
It was also necessary to be more careful about boundary nodes when iterating across successors in the dependence graph because the loop exit branch is now a non-artificial successor to instructions in the graph. In additional, schedules with physical use/def pairs in the same cycle should be treated as creating an invalid schedule because the scheduling logic doesn't respect physical register dependence once scheduled to the same cycle.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D122672
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fa49021c |
| 28-Apr-2022 |
David Penry <david.penry@arm.com> |
Revert "[CodeGen][ARM] Enable Swing Module Scheduling for ARM"
This reverts commit 28d09bbbc3d09c912b54a4d5edb32cab7de32a6f while I investigate a buildbot failure.
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28d09bbb |
| 29-Mar-2022 |
David Penry <david.penry@arm.com> |
[CodeGen][ARM] Enable Swing Module Scheduling for ARM
This patch permits Swing Modulo Scheduling for ARM targets turns it on by default for the Cortex-M7. The t2Bcc instruction is recognized as a l
[CodeGen][ARM] Enable Swing Module Scheduling for ARM
This patch permits Swing Modulo Scheduling for ARM targets turns it on by default for the Cortex-M7. The t2Bcc instruction is recognized as a loop-ending branch.
MachinePipeliner is extended by adding support for "unpipelineable" instructions. These instructions are those which contribute to the loop exit test; in the SMS papers they are removed before creating the dependence graph and then inserted into the final schedule of the kernel and prologues. Support for these instructions was not previously necessary because current targets supporting SMS have only supported it for hardware loop branches, which have no loop-exit-contributing instructions in the loop body.
The current structure of the MachinePipeliner makes it difficult to remove/exclude these instructions from the dependence graph. Therefore, this patch leaves them in the graph, but adds a "normalization" method which moves them in the schedule to stage 0, which causes them to appear properly in kernel and prologues.
It was also necessary to be more careful about boundary nodes when iterating across successors in the dependence graph because the loop exit branch is now a non-artificial successor to instructions in the graph. In additional, schedules with physical use/def pairs in the same cycle should be treated as creating an invalid schedule because the scheduling logic doesn't respect physical register dependence once scheduled to the same cycle.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D122672
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449ef2fc |
| 04-Apr-2022 |
Thomas Preud'homme <thomasp@graphcore.ai> |
[Pipeliner] Fix comment typo
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989f1c72 |
| 15-Mar-2022 |
serge-sans-paille <sguelton@redhat.com> |
Cleanup codegen includes
This is a (fixed) recommit of https://reviews.llvm.org/D121169
after: 1061034926 before: 1063332844
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-in
Cleanup codegen includes
This is a (fixed) recommit of https://reviews.llvm.org/D121169
after: 1061034926 before: 1063332844
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121681
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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3 |
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a278250b |
| 10-Mar-2022 |
Nico Weber <thakis@chromium.org> |
Revert "Cleanup codegen includes"
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20. Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang, and many LLVM tests, see comments on https:/
Revert "Cleanup codegen includes"
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20. Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang, and many LLVM tests, see comments on https://reviews.llvm.org/D121169
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7f230fee |
| 07-Mar-2022 |
serge-sans-paille <sguelton@redhat.com> |
Cleanup codegen includes
after: 1061034926 before: 1063332844
Differential Revision: https://reviews.llvm.org/D121169
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67c14d5c |
| 09-Mar-2022 |
Thomas Preud'homme <thomasp@graphcore.ai> |
[MachinePipeliner] Fix isPseduo typo.
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Revision tags: llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2 |
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bb6447a7 |
| 13-Dec-2021 |
Kazu Hirata <kazu@google.com> |
[llvm] Use llvm::reverse (NFC)
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b0127424 |
| 09-Dec-2021 |
Mircea Trofin <mtrofin@google.com> |
[NFC] Rename MachineFunction::deleteMachineInstr (coding style)
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c4a8928b |
| 06-Dec-2021 |
Kazu Hirata <kazu@google.com> |
[CodeGen] Use range-based for loops (NFC)
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