[MIR] Adding support for Named Virtual Registers in MIR.

llvm-svn: 328887

[CodeGen] Fixed unreachable with -print-machineinstrs and custom pseudo source value

Summary:
Rev 327580 "[CodeGen] Use MIR syntax for MachineMemOperand printing"
broke -print-machineinstrs for us o

[CodeGen] Fixed unreachable with -print-machineinstrs and custom pseudo source value

Summary:
Rev 327580 "[CodeGen] Use MIR syntax for MachineMemOperand printing"
broke -print-machineinstrs for us on AMDGPU, because we have custom
pseudo source values, and MIR serialization does not implement that.

This commit at least restores the functionality of -print-machineinstrs,
even if it does not properly implement the missing MIR serialization
functionality.

Differential Revision: https://reviews.llvm.org/D44871

Change-Id: I44961c0b90bf6d48c01484ed7a4e466fd300db66
llvm-svn: 328668

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[CodeGen] Use MIR syntax for MachineMemOperand printing

Get rid of the "; mem:" suffix and use the one we use in MIR: ":: (load 2)".

rdar://38163529

Differential Revision: https://reviews.llvm.org

[CodeGen] Use MIR syntax for MachineMemOperand printing

Get rid of the "; mem:" suffix and use the one we use in MIR: ":: (load 2)".

rdar://38163529

Differential Revision: https://reviews.llvm.org/D42377

llvm-svn: 327580

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[MachineOperand][Target] MachineOperand::isRenamable semantics changes

Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers. T

[MachineOperand][Target] MachineOperand::isRenamable semantics changes

Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers. This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.

Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).

Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.

Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.

Clear the IsRenamable bit when changing an operand's register value.

Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.

Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.

Reviewers: qcolombet, MatzeB

Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D43042

llvm-svn: 325931

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[CodeGen][NFC] Rename IsVerbose to IsStandalone in Machine*::print

Committed r322867 too soon.

Differential Revision: https://reviews.llvm.org/D42239

llvm-svn: 322868

[CodeGen] Print RegClasses on MI in verbose mode

r322086 removed the trailing information describing reg classes for each
register.

This patch adds printing reg classes next to every register when

[CodeGen] Print RegClasses on MI in verbose mode

r322086 removed the trailing information describing reg classes for each
register.

This patch adds printing reg classes next to every register when
individual operands/instructions/basic blocks are printed. In the case
of dumping MIR or printing a full function, by default don't print it.

Differential Revision: https://reviews.llvm.org/D42239

llvm-svn: 322867

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[CodeGen][NFC] Correct case for printSubRegIdx

llvm-svn: 322541

[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.

Planning to add support for named vregs. This puts is in a conundrum since
physregs are named as well. To rectify this we ne

[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.

Planning to add support for named vregs. This puts is in a conundrum since
physregs are named as well. To rectify this we need to use a sigil other than
'%' for physregs in MIR. We've settled on using '$' for physregs but first we
must repurpose it from external symbols using it, which is what this commit is
all about. We think '&' will have familiar semantics for C/C++ users.

llvm-svn: 322146

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[CodeGen] Move printing MO_BlockAddress operands to MachineOperand::print

Work towards the unification of MIR and debug output by refactoring the
interfaces.

llvm-svn: 321113

[CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::print

Work towards the unification of MIR and debug output by refactoring the
interfaces.

llvm-svn: 321112

[CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::print

Work towards the unification of MIR and debug output by refactoring the
interfaces.

Also add support for printing with a nul

[CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::print

Work towards the unification of MIR and debug output by refactoring the
interfaces.

Also add support for printing with a null TargetIntrinsicInfo and no
MachineFunction.

llvm-svn: 321111

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[CodeGen] Move printing MO_FPImmediate operands to MachineOperand::print

Work towards the unification of MIR and debug output by refactoring the
interfaces.

llvm-svn: 321110

[CodeGen] Refactor printOffset from MO and MIRPrinter

llvm-svn: 321109

[CodeGen] Move printing MO_CFIIndex operands to MachineOperand::print

Work towards the unification of MIR and debug output by refactoring the
interfaces.

Before this patch we printed "<call frame i

[CodeGen] Move printing MO_CFIIndex operands to MachineOperand::print

Work towards the unification of MIR and debug output by refactoring the
interfaces.

Before this patch we printed "<call frame instruction>" in the debug
output.

llvm-svn: 321084

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[CodeGen] Print stack object references as %(fixed-)stack.0 in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`%stack.0` instead of `<fi#0>`, and `%fixed-

[CodeGen] Print stack object references as %(fixed-)stack.0 in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`%stack.0` instead of `<fi#0>`, and `%fixed-stack.0` instead of
`<fi#-4>` (supposing there are 4 fixed stack objects).

Only debug syntax is affected.

Differential Revision: https://reviews.llvm.org/D41027

llvm-svn: 320827

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[MIR] Add support for missing CFI directives

The following CFI directives are suported by MC but not by MIR:

* .cfi_rel_offset
* .cfi_adjust_cfa_offset
* .cfi_escape
* .cfi_remember_state
* .cfi_re

[MIR] Add support for missing CFI directives

The following CFI directives are suported by MC but not by MIR:

* .cfi_rel_offset
* .cfi_adjust_cfa_offset
* .cfi_escape
* .cfi_remember_state
* .cfi_restore_state
* .cfi_undefined
* .cfi_register
* .cfi_window_save

Add support for printing, parsing and update tests.

Differential Revision: https://reviews.llvm.org/D41230

llvm-svn: 320819

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[CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`<mcsymbol sym>` instead of `<MCSym=sym>`.

Only deb

[CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`<mcsymbol sym>` instead of `<MCSym=sym>`.

Only debug syntax is affected.

llvm-svn: 320685

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[CodeGen] Move printing MO_Metadata operands to MachineOperand::print

Work towards the unification of MIR and debug output by refactoring the
interfaces.

llvm-svn: 320684

[CodeGen] Print live-out register lists as liveout(...) in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`liveout(...)` instead of `<regliveout>`.

Only

[CodeGen] Print live-out register lists as liveout(...) in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`liveout(...)` instead of `<regliveout>`.

Only debug syntax is affected.

llvm-svn: 320683

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[CodeGen] Print global addresses as @foo in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`@foo` instead of `<ga:@foo>`.

Also print target flags in the

[CodeGen] Print global addresses as @foo in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`@foo` instead of `<ga:@foo>`.

Also print target flags in the MIR format since most of them are used on
global address operands.

Only debug syntax is affected.

llvm-svn: 320682

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[CodeGen] Print external symbols as $symbol in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`$symbol` instead of `<es:symbol>`.

Only debug syntax is af

[CodeGen] Print external symbols as $symbol in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`$symbol` instead of `<es:symbol>`.

Only debug syntax is affected.

llvm-svn: 320681

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[CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug output

Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`.

Only de

[CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug output

Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`.

Only debug syntax is affected.

llvm-svn: 320566

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[CodeGen] Print target index operands as target-index(target-specific) + 8 in both MIR and debug output

Work towards the unification of MIR and debug output by printing `target-index(target-specific

[CodeGen] Print target index operands as target-index(target-specific) + 8 in both MIR and debug output

Work towards the unification of MIR and debug output by printing `target-index(target-specific) + 8` instead of `<ti#0+8>` and `target-index(target-specific) + 8` instead of `<ti#0-8>`.

Only debug syntax is affected.

llvm-svn: 320565

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[CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`%const.0 + 8` instead of `<cp#0+8>` and `%

[CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of
`<cp#0-8>`.

Only debug syntax is affected.

Differential Revision: https://reviews.llvm.org/D41116

llvm-svn: 320564

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[MachineOperand][MIR] Add isRenamable to MachineOperand.

Summary:
Add isRenamable() predicate to MachineOperand. This predicate can be
used by machine passes after register allocation to determine

[MachineOperand][MIR] Add isRenamable to MachineOperand.

Summary:
Add isRenamable() predicate to MachineOperand. This predicate can be
used by machine passes after register allocation to determine whether it
is safe to rename a given register operand. Register operands that
aren't marked as renamable may be required to be assigned their current
register to satisfy constraints that are not captured by the machine
IR (e.g. ABI or ISA constraints).

Reviewers: qcolombet, MatzeB, hfinkel

Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D39400

llvm-svn: 320503

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