another selectto

llvm-svn: 25548

add stacksave/stackrestore nodes

llvm-svn: 25270

Add bswap, rotl, and rotr nodes
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them

llvm-svn: 25222

Grammer correction.

llvm-svn: 25106

Added initial support for DEBUG_LABEL allowing debug specific labels to be
inserted in the code.

llvm-svn: 25104

Add unique id to debug location for debug label use (work in progress.)

llvm-svn: 25096

improve comment: mention vectors

llvm-svn: 24971

add a new node

llvm-svn: 24969

remove a dead node

llvm-svn: 24966

Added source file/line correspondence for dwarf (PowerPC only at this point.)

llvm-svn: 24748

Teach the SelectionDAG ISel how to turn ConstantPacked values into
constant nodes with vector types. Also teach the asm printer how to print
ConstantPacked constant pool entries. This allows us to

Teach the SelectionDAG ISel how to turn ConstantPacked values into
constant nodes with vector types. Also teach the asm printer how to print
ConstantPacked constant pool entries. This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.

LCPI1_0: <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
.space 4
.space 4
.space 4
.long 1065353216 ; float 1
.text
.align 4
.globl _foo
_foo:
lis r2, ha16(LCPI1_0)
la r2, lo16(LCPI1_0)(r2)
li r4, 0
lvx v0, r4, r2
lvx v1, r4, r3
vaddfp v0, v1, v0
stvx v0, r4, r3
blr

For the llvm code:

void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
store <4 x float> %tmp2, <4 x float> *%a
ret void
}

llvm-svn: 24616

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Added an index field to GlobalAddressSDNode so it can represent X+12, etc.

llvm-svn: 24523

Add support for a new STRING and LOCATION node for line number support, patch
contributed by Daniel Berlin, with a few cleanups here and there by me.

llvm-svn: 24512

Check in code to scalarize arbitrarily wide packed types for some simple
vector operations (load, add, sub, mul).

This allows us to codegen:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x

Check in code to scalarize arbitrarily wide packed types for some simple
vector operations (load, add, sub, mul).

This allows us to codegen:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}

on ppc as:
_foo:
lfs f0, 12(r3)
lfs f1, 8(r3)
lfs f2, 4(r3)
lfs f3, 0(r3)
fadds f0, f0, f0
fadds f1, f1, f1
fadds f2, f2, f2
fadds f3, f3, f3
stfs f0, 12(r3)
stfs f1, 8(r3)
stfs f2, 4(r3)
stfs f3, 0(r3)
blr

llvm-svn: 24484

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add a new node type

llvm-svn: 24436

Teach LLVM how to scalarize packed types. Currently, this only works on
packed types with an element count of 1, although more generic support is
coming. This allows LLVM to turn the following code

Teach LLVM how to scalarize packed types. Currently, this only works on
packed types with an element count of 1, although more generic support is
coming. This allows LLVM to turn the following code:

void %foo(<1 x float> * %a) {
entry:
%tmp1 = load <1 x float> * %a;
%tmp2 = add <1 x float> %tmp1, %tmp1
store <1 x float> %tmp2, <1 x float> *%a
ret void
}

Into:

_foo:
lfs f0, 0(r3)
fadds f0, f0, f0
stfs f0, 0(r3)
blr

llvm-svn: 24416

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added a chain output

llvm-svn: 24306

Add support for a cycle counter intrinsic. As basically all processors have
this and have it in about the same form, I think this makes sense.
on X86, you do a RDTSC (64bit result, from any ring sin

Add support for a cycle counter intrinsic. As basically all processors have
this and have it in about the same form, I think this makes sense.
on X86, you do a RDTSC (64bit result, from any ring since the P5MMX)
on Alpha, you do a RDCC
on PPC, there is a sequence which may or may not work depending on how things
are setup by the OS. Or something like that. Maybe someone who knows PPC
can add support. Something about the time base register.
on Sparc, you read %tick, which in some solaris versions (>=8) is readable by
userspace
on IA64 read ar.itc

So I think the ulong is justified since all of those are 64bit.
Support is slighly flaky on old chips (P5 and lower) and sometimes
depends on OS (PPC, Sparc). But for modern OS/Hardware (aka this decade),
we should be ok.

I am still not sure what to do about lowering. I can either see a lower to 0, to
gettimeofday (or the target os equivalent), or loudly complaining and refusing to
continue.

I am commiting an Alpha implementation. I will add the X86 implementation if I
have to (I have use of it in the near future), but if someone who knows that
backend (and the funky multi-register results) better wants to add it, it would
take them a lot less time ;)

TODO: better lowering and legalizing, and support more platforms
llvm-svn: 24299

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Switch the allnodes list from a vector of pointers to an ilist of nodes.
This eliminates the vector, allows constant time removal of a node from
a graph, and makes iteration over the all nodes list s

Switch the allnodes list from a vector of pointers to an ilist of nodes.
This eliminates the vector, allows constant time removal of a node from
a graph, and makes iteration over the all nodes list stable when adding
nodes to the graph.

llvm-svn: 24262

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Change the ValueList array for each node to be shared instead of individually
allocated. Further, in the common case where a node has a single value, just
reference an element from a small array. T

Change the ValueList array for each node to be shared instead of individually
allocated. Further, in the common case where a node has a single value, just
reference an element from a small array. This is a small compile-time wi.

llvm-svn: 24250

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Switch the operandlist/valuelist from being vectors to being just an array.
This saves 12 bytes from SDNode, but doesn't speed things up substantially
(our graphs apparently already fit within the ca

Switch the operandlist/valuelist from being vectors to being just an array.
This saves 12 bytes from SDNode, but doesn't speed things up substantially
(our graphs apparently already fit within the cache on my g5). In any case
this reduces memory usage.

llvm-svn: 24248

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add TargetExternalSymbol

llvm-svn: 23886

add a helper class

llvm-svn: 23633

Add FP versions of the binary operators, keeping the int and fp worlds seperate.

llvm-svn: 23506

Add a new ANY_EXTEND node, which operates like an extension but has undefined
top bits.

llvm-svn: 23200