History log of /llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h (Results 76 – 100 of 866)
Revision (<<< Hide revision tags) (Show revision tags >>>) Date Author Comments
Revision tags: llvmorg-14.0.0-rc1, llvmorg-15-init
# 152d61a8 31-Jan-2022 Kazu Hirata <kazu@google.com>

[llvm] Use = default (NFC)


Revision tags: llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2
# 88ecdd30 05-Jan-2022 Craig Topper <craig.topper@sifive.com>

[LegalizeTypes] Remove IsVP argument from type legalization methods. NFC

We can either check the opcode or number of operands or use
ISD::isVPOpcode inside the methods.

In some places I've used num

[LegalizeTypes] Remove IsVP argument from type legalization methods. NFC

We can either check the opcode or number of operands or use
ISD::isVPOpcode inside the methods.

In some places I've used number of operands figuring that it is
cheaper than isVPOpcode. I've included isVPOpcode in an assert to
verify.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D116578

show more ...


Revision tags: llvmorg-13.0.1-rc1
# 4c484f11 16-Nov-2021 River Riddle <riddleriver@gmail.com>

[llvm] Add a SFINAE template parameter to DenseMapInfo

This allows for using SFINAE partial specialization for DenseMapInfo.
In MLIR, this is particularly useful as it will allow for defining partia

[llvm] Add a SFINAE template parameter to DenseMapInfo

This allows for using SFINAE partial specialization for DenseMapInfo.
In MLIR, this is particularly useful as it will allow for defining partial
specializations that support all Attribute, Op, and Type classes without
needing to specialize DenseMapInfo for each individual class.

Differential Revision: https://reviews.llvm.org/D113641

show more ...


# ed80761b 10-Nov-2021 Simon Pilgrim <llvm-dev@redking.me.uk>

[DAG] Split BuildVectorSDNode::getConstantRawBits into BuildVectorSDNode::recastRawBits helper. NFC.

NFC refactor of D113351, pulling out the APInt split/merge code from the BuildVectorSDNode bits e

[DAG] Split BuildVectorSDNode::getConstantRawBits into BuildVectorSDNode::recastRawBits helper. NFC.

NFC refactor of D113351, pulling out the APInt split/merge code from the BuildVectorSDNode bits extraction into a BuildVectorSDNode::recastRawBits helper. This is to allow us to reuse the code when we're packing constant folded APInt data back together.

show more ...


# f60d3ec0 08-Nov-2021 Simon Pilgrim <llvm-dev@redking.me.uk>

[DAG] Add BuildVectorSDNode::getConstantRawBits helper

We have several places where we need to extract the raw bits data from a BUILD_VECTOR node, so consolidate this to a single helper function tha

[DAG] Add BuildVectorSDNode::getConstantRawBits helper

We have several places where we need to extract the raw bits data from a BUILD_VECTOR node, so consolidate this to a single helper function that handles Undefs and Integer/FP constants, including implicit truncation.

This should make it easier to extend D113202 to handle more constant folding of bitcasted constant data.

Differential Revision: https://reviews.llvm.org/D113351

show more ...


# e2d5a380 12-Oct-2021 Roger Ferrer Ibanez <rofirrim@gmail.com>

[SelectionDAG] Fix typo in VPLoadStoreSDNode

There is no code that uses this base class yet, hence the typo went
unnoticed when this class was added in D105871

Differential Revision: https://review

[SelectionDAG] Fix typo in VPLoadStoreSDNode

There is no code that uses this base class yet, hence the typo went
unnoticed when this class was added in D105871

Differential Revision: https://reviews.llvm.org/D110930

show more ...


Revision tags: llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3
# 9af8f1b1 09-Sep-2021 Craig Topper <craig.topper@sifive.com>

[SelectionDAG] Add isZero/isAllOnes methods to ConstantSDNode.

Soft deprecrate isNullValue/isAllOnesValue and update in tree
callers. This matches the changes to the APInt interface from
D109483.

R

[SelectionDAG] Add isZero/isAllOnes methods to ConstantSDNode.

Soft deprecrate isNullValue/isAllOnesValue and update in tree
callers. This matches the changes to the APInt interface from
D109483.

Reviewed By: lattner

Differential Revision: https://reviews.llvm.org/D109535

show more ...


# a40599c9 06-Sep-2021 Fraser Cormack <fraser@codeplay.com>

[SelectionDAG][VP] Fix MemSDNode::getBasePtr

Found while working on D108987. When interpreting VP nodes as
`MemSDNode` nodes, this function would return the incorrect indices.
This was due to `VP_GA

[SelectionDAG][VP] Fix MemSDNode::getBasePtr

Found while working on D108987. When interpreting VP nodes as
`MemSDNode` nodes, this function would return the incorrect indices.
This was due to `VP_GATHER` and having no "passthru", and both
`VP_GATHER` and `VP_SCATTER` having their mask operands *after* the base
pointer, unlike `MGATHER` and `MSCATTER`.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D109308

show more ...


# 524ded7d 31-Aug-2021 Hussain Kadhem <hussain@ibm.com>

[VP] implementation of sdag support for VP memory intrinsics

Followup to D99355: SDAG support for vector-predicated load/store/gather/scatter.

Reviewed By: frasercrmck

Differential Revision: https

[VP] implementation of sdag support for VP memory intrinsics

Followup to D99355: SDAG support for vector-predicated load/store/gather/scatter.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D105871

show more ...


Revision tags: llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init
# 4f71f59b 02-Jul-2021 Juneyoung Lee <aqjune@gmail.com>

[DAGCombiner] Fold SETCC(FREEZE(x),const) to FREEZE(SETCC(x,const)) if SETCC is used by BRCOND

This patch adds a peephole optimization `SETCC(FREEZE(x),const)` => `FREEZE(SETCC(x,const))`
if the SET

[DAGCombiner] Fold SETCC(FREEZE(x),const) to FREEZE(SETCC(x,const)) if SETCC is used by BRCOND

This patch adds a peephole optimization `SETCC(FREEZE(x),const)` => `FREEZE(SETCC(x,const))`
if the SETCC is only used by BRCOND.

Combined with `BRCOND(FREEZE(X)) => BRCOND(X)`, this leads to a nice improvement in the generated assembly when x is a masked loaded value.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D105344

show more ...


# f15c39ba 19-Jul-2021 Kazu Hirata <kazu@google.com>

[CodeGen] Remove isNON_TRUNCStore and isTRUNCStore (NFC)

The last use of isNON_TRUNCStore was removed on Oct 10, 2018 in commit
07acc992dc39edfccc5a4b773c3dcf8a5bf6d893.

isTRUNCStore seems to be un

[CodeGen] Remove isNON_TRUNCStore and isTRUNCStore (NFC)

The last use of isNON_TRUNCStore was removed on Oct 10, 2018 in commit
07acc992dc39edfccc5a4b773c3dcf8a5bf6d893.

isTRUNCStore seems to be unused for at least 10 years.

show more ...


# d21a35ac 01-Jul-2021 Hussain Kadhem <hussain@ibm.com>

[VP] Implementation of intrinsic and SDNode definitions for VP load, store, gather, scatter.

This patch adds intrinsic definitions and SDNodes for predicated
load/store/gather/scatter, based on the

[VP] Implementation of intrinsic and SDNode definitions for VP load, store, gather, scatter.

This patch adds intrinsic definitions and SDNodes for predicated
load/store/gather/scatter, based on the work done in D57504.

Reviewed By: simoll, craig.topper

Differential Revision: https://reviews.llvm.org/D99355

show more ...


Revision tags: llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3
# 74909e4b 21-Jun-2021 Eli Friedman <efriedma@quicinc.com>

Rename MachineMemOperand::getOrdering -> getSuccessOrdering.

Since this method can apply to cmpxchg operations, make sure it's clear
what value we're actually retrieving. This will help ensure we d

Rename MachineMemOperand::getOrdering -> getSuccessOrdering.

Since this method can apply to cmpxchg operations, make sure it's clear
what value we're actually retrieving. This will help ensure we don't
accidentally ignore the failure ordering of cmpxchg in the future.

We could potentially introduce a getOrdering() method on AtomicSDNode
that asserts the operation isn't cmpxchg, but not sure that's
worthwhile.

Differential Revision: https://reviews.llvm.org/D103338

show more ...


Revision tags: llvmorg-12.0.1-rc2
# 81f7607f 01-Jun-2021 Sean Fertile <sd.fertile@gmail.com>

[PowerPC][AIX} FIx AIX bootstrap build.

A recent patch:
https://reviews.llvm.org/rGe0921655b1ff8d4ba7c14be59252fe05b705920e
changed clangs AIX bitfield handling to use 4-byte bitfield containers,
ma

[PowerPC][AIX} FIx AIX bootstrap build.

A recent patch:
https://reviews.llvm.org/rGe0921655b1ff8d4ba7c14be59252fe05b705920e
changed clangs AIX bitfield handling to use 4-byte bitfield containers,
matching XLs behavior. This change triggers static assert failures when
bootstrapping. Change the macro we check to enable bitfield packing on
AIX to `__clang__` which is defined by both xlclang and clang.

Differential Revision: https://reviews.llvm.org/D103474

show more ...


# 0b3b0a72 27-May-2021 Eli Friedman <efriedma@quicinc.com>

[AArch64][RISCV] Make sure isel correctly honors failure orderings.

If a cmpxchg specifies acquire or seq_cst on failure, make sure we
generate code consistent with that ordering even if the success

[AArch64][RISCV] Make sure isel correctly honors failure orderings.

If a cmpxchg specifies acquire or seq_cst on failure, make sure we
generate code consistent with that ordering even if the success ordering
is not acquire/seq_cst.

At one point, it was ambiguous whether this sort of construct was valid,
but the C++ standad and LLVM now accept arbitrary combinations of
success/failure orderings.

This doesn't address the corresponding issue in AtomicExpand. (This was
reported as https://bugs.llvm.org/show_bug.cgi?id=33332 .)

Fixes https://bugs.llvm.org/show_bug.cgi?id=50512.

Differential Revision: https://reviews.llvm.org/D103284

show more ...


Revision tags: llvmorg-12.0.1-rc1
# e805b7c2 07-May-2021 Guillaume Chatelet <gchatelet@google.com>

[llvm][NFC] Remove remaining deprecated alignment functions from CodeGen

Differential Revision: https://reviews.llvm.org/D102058


# 0a92aff7 12-Apr-2021 Hamza Sood <hamza_sood@me.com>

Replace uses of std::iterator with explicit using

This patch removes all uses of `std::iterator`, which was deprecated in C++17.
While this isn't currently an issue while compiling LLVM, it's useful

Replace uses of std::iterator with explicit using

This patch removes all uses of `std::iterator`, which was deprecated in C++17.
While this isn't currently an issue while compiling LLVM, it's useful for those using LLVM as a library.

For some reason there're a few places that were seemingly able to use `std` functions unqualified, which no longer works after this patch. I've updated those places, but I'm not really sure why it worked in the first place.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D67586

show more ...


Revision tags: llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4
# eb3d9f2e 28-Mar-2021 Florian Hahn <flo@fhahn.com>

[SelDag] Add isIntOrFPConstant helper function.

This patch adds a new isIntOrFPConstant helper function to check if a
SDValue is a integer of FP constant. This pattern is used in various
places.

T

[SelDag] Add isIntOrFPConstant helper function.

This patch adds a new isIntOrFPConstant helper function to check if a
SDValue is a integer of FP constant. This pattern is used in various
places.

There also are places that incorrectly just check for integer constants,
e.g. D99384, so hopefully this helper will help people avoid that issue.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D99428

show more ...


Revision tags: llvmorg-12.0.0-rc3
# 415c67ba 02-Mar-2021 Sanjay Patel <spatel@rotateright.com>

[SDAG] allow partial undef vector constants with select->logic folds

This is an enhancement suggested in the original review/commit:
D97730 / 7fce3322a283


Revision tags: llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3
# c18231e3 03-Feb-2021 Kazu Hirata <kazu@google.com>

[CodeGen] Drop unnecessary const from return types (NFC)

Identified with const-return-type.


Revision tags: llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2
# 6de48655 21-Jan-2021 Kazu Hirata <kazu@google.com>

[llvm] Use hasSingleElement (NFC)


Revision tags: llvmorg-11.1.0-rc1
# de373ef7 06-Jan-2021 Fraser Cormack <fraser@codeplay.com>

[SelectionDAG] Extend immAll(Ones|Zeros)V to handle ISD::SPLAT_VECTOR

The TableGen immAllOnesV and immAllZerosV helpers implicitly wrapped the
ISD::isBuildVectorAll(Ones|Zeros) helper functions. Thi

[SelectionDAG] Extend immAll(Ones|Zeros)V to handle ISD::SPLAT_VECTOR

The TableGen immAllOnesV and immAllZerosV helpers implicitly wrapped the
ISD::isBuildVectorAll(Ones|Zeros) helper functions. This was inhibiting
their use for targets such as RISC-V which use ISD::SPLAT_VECTOR. In
particular, RISC-V had to define its own 'vnot' fragment.

In order to extend the scope of these nodes to include support for
ISD::SPLAT_VECTOR, two new ISD predicate functions have been introduced:
ISD::isConstantSplatVectorAll(Ones|Zeros). These effectively supersede
the older "isBuildVector" predicates, which are now simple wrappers for
the new functions. They pass a defaulted boolean toggle which preserves
the old behaviour. It is hoped that in time all call-sites can be ported
to the "isConstantSplatVector" functions.

While the use of ISD::isBuildVectorAll(Ones|Zeros) has not changed, the
behaviour of the TableGen immAll(Ones|Zeros)V **has**. To test the new
functionality, the custom RISC-V TableGen fragment has been removed and
replaced with the built-in 'vnot'. To test their use as pattern-roots, two
splat patterns have been updated accordingly.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94223

show more ...


Revision tags: llvmorg-11.0.1, llvmorg-11.0.1-rc2
# d2ed9d6b 15-Dec-2020 Reid Kleckner <rnk@google.com>

Revert "ADT: Migrate users of AlignedCharArrayUnion to std::aligned_union_t, NFC"

We determined that the MSVC implementation of std::aligned* isn't suited
to our needs. It doesn't support 16 byte al

Revert "ADT: Migrate users of AlignedCharArrayUnion to std::aligned_union_t, NFC"

We determined that the MSVC implementation of std::aligned* isn't suited
to our needs. It doesn't support 16 byte alignment or higher, and it
doesn't really guarantee 8 byte alignment. See
https://github.com/microsoft/STL/issues/1533

Also reverts "ADT: Change AlignedCharArrayUnion to an alias of std::aligned_union_t, NFC"

Also reverts "ADT: Remove AlignedCharArrayUnion, NFC" to bring back
AlignedCharArrayUnion.

This reverts commit 4d8bf870a82765eb0d4fe53c82f796b957c05954.

This reverts commit d10f9863a5ac1cb681af07719650c44b48f289ce.

This reverts commit 4b5dc150b9862271720b3d56a3e723a55dd81838.

show more ...


# 4519ff4b 09-Dec-2020 Kerry McLaughlin <kerry.mclaughlin@arm.com>

[SVE][CodeGen] Add the ExtensionType flag to MGATHER

Adds the ExtensionType flag, which reflects the LoadExtType of a MaskedGatherSDNode.
Also updated SelectionDAGDumper::print_details so that detai

[SVE][CodeGen] Add the ExtensionType flag to MGATHER

Adds the ExtensionType flag, which reflects the LoadExtType of a MaskedGatherSDNode.
Also updated SelectionDAGDumper::print_details so that details of the gather
load (is signed, is scaled & extension type) are printed.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D91084

show more ...


# d10f9863 02-Dec-2020 Duncan P. N. Exon Smith <dexonsmith@apple.com>

ADT: Migrate users of AlignedCharArrayUnion to std::aligned_union_t, NFC

Prepare to delete `AlignedCharArrayUnion` by migrating its users over to
`std::aligned_union_t`.

I will delete `AlignedCharA

ADT: Migrate users of AlignedCharArrayUnion to std::aligned_union_t, NFC

Prepare to delete `AlignedCharArrayUnion` by migrating its users over to
`std::aligned_union_t`.

I will delete `AlignedCharArrayUnion` and its tests in a follow-up
commit so that it's easier to revert in isolation in case some
downstream wants to keep using it.

Differential Revision: https://reviews.llvm.org/D92516

show more ...


12345678910>>...35