Revision tags: llvmorg-3.8.0-rc3 |
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e6154ffb |
| 17-Feb-2016 |
Nico Weber <nicolasweber@gmx.de> |
Revert r261070, it caused PR26652 / PR26653.
llvm-svn: 261127
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bbd4e3b4 |
| 17-Feb-2016 |
Cong Hou <congh@google.com> |
Detecte vector reduction operations just before instruction selection.
This patch detects vector reductions before instruction selection. Vector reductions are vectorized reduction operations, and f
Detecte vector reduction operations just before instruction selection.
This patch detects vector reductions before instruction selection. Vector reductions are vectorized reduction operations, and for such operations we have freedom to reorganize the elements of the result as long as the reduction of them stay unchanged. This will enable some reduction pattern recognition during instruction combine such as SAD/dot-product on X86. A flag is added to SDNodeFlags to mark those vector reduction nodes to be checked during instruction combine.
To detect those vector reductions, we search def-use chains starting from the given instruction, and check if all uses fall into two categories:
1. Reduction with another vector. 2. Reduction on all elements.
in which 2 is detected by recognizing the pattern that the loop vectorizer generates to reduce all elements in the vector outside of the loop, which includes several ShuffleVector and one ExtractElement instructions.
Differential revision: http://reviews.llvm.org/D15250
llvm-svn: 261070
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Revision tags: llvmorg-3.8.0-rc2, llvmorg-3.8.0-rc1 |
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4e9b2a60 |
| 15-Jan-2016 |
Dan Gohman <dan433584@gmail.com> |
[SelectionDAG] CSE nodes with differing SDNodeFlags
In the optimizer (GVN etc.) when eliminating redundant nodes with different flags, the flags are ignored for the purposes of testing for congruenc
[SelectionDAG] CSE nodes with differing SDNodeFlags
In the optimizer (GVN etc.) when eliminating redundant nodes with different flags, the flags are ignored for the purposes of testing for congruence, and then intersected for the purposes of producing a result that supports the union of all the uses. This commit makes SelectionDAG's CSE do the same thing, allowing it to CSE nodes in more cases. This fixes PR26063.
Differential Revision: http://reviews.llvm.org/D15957
llvm-svn: 257940
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6015f5c8 |
| 15-Dec-2015 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Type legalizer for masked gather and scatter intrinsics.
Full type legalizer that works with all vectors length - from 2 to 16, (i32, i64, float, double).
This intrinsic, for example void @llvm.mas
Type legalizer for masked gather and scatter intrinsics.
Full type legalizer that works with all vectors length - from 2 to 16, (i32, i64, float, double).
This intrinsic, for example void @llvm.masked.scatter.v2f32(<2 x float>%data , <2 x float*>%ptrs , i32 align , <2 x i1>%mask ) requires type widening for data and type promotion for mask.
Differential Revision: http://reviews.llvm.org/D13633
llvm-svn: 255629
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15576e1c |
| 06-Dec-2015 |
Craig Topper <craig.topper@gmail.com> |
Use make_range to reduce mentions of iterator type. NFC
llvm-svn: 254872
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4824adaa |
| 06-Dec-2015 |
Craig Topper <craig.topper@gmail.com> |
Minor formatting fix. NFC
llvm-svn: 254871
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Revision tags: llvmorg-3.7.1 |
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314ee042 |
| 25-Nov-2015 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
Expose isXxxConstant() functions from SelectionDAGNodes.h (NFC)
Summary: Many target lowerings copy-paste the code to test SDValues for known constants. This code can instead be shared in SelectionD
Expose isXxxConstant() functions from SelectionDAGNodes.h (NFC)
Summary: Many target lowerings copy-paste the code to test SDValues for known constants. This code can instead be shared in SelectionDAG.cpp, and reused in the targets.
Reviewers: MatzeB, andreadb, tstellarAMD
Subscribers: arsenm, jyknight, llvm-commits
Differential Revision: http://reviews.llvm.org/D14945
llvm-svn: 254085
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Revision tags: llvmorg-3.7.1-rc2 |
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6f2a59b7 |
| 19-Nov-2015 |
Reid Kleckner <rnk@google.com> |
Initialize PersistentId for HandleSDNode, as these will never be inserted into the DAG
llvm-svn: 253524
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Revision tags: llvmorg-3.7.1-rc1 |
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df1ec556 |
| 24-Oct-2015 |
Davide Italiano <davide@freebsd.org> |
[CodeGen] Get rid of NDEBUG to ensure structure stability.
I think it's fine to keep this fields around in terms of overhead, I wasn't able to measure any substantial regression while running the te
[CodeGen] Get rid of NDEBUG to ensure structure stability.
I think it's fine to keep this fields around in terms of overhead, I wasn't able to measure any substantial regression while running the test suite, but, in case this causes some regression I'm ready to revert and work on an alternative solution. This was tested building with clang/gcc both in Debug and Release mode and passes the test-suite.
llvm-svn: 251209
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bacc7ba7 |
| 15-Oct-2015 |
Benjamin Kramer <benny.kra@googlemail.com> |
[SelectionDAG] Remove dead code. NFC.
Carefully selected parts without deleting graph stuff and dumping methods.
llvm-svn: 250434
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169865ff |
| 07-Oct-2015 |
Chad Rosier <mcrosier@codeaurora.org> |
[ARM] Promote helper function to SelectionDAG.
I'll be using the function in a similar combine for AArch64. The helper was also improved to handle undef values.
Part of http://reviews.llvm.org/D13
[ARM] Promote helper function to SelectionDAG.
I'll be using the function in a similar combine for AArch64. The helper was also improved to handle undef values.
Part of http://reviews.llvm.org/D13442
llvm-svn: 249572
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5bdde3bd |
| 05-Oct-2015 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Reformat partially.
llvm-svn: 249288
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f68eb2d1 |
| 05-Oct-2015 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Trailing whitespaces.
llvm-svn: 249286
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07609eab |
| 05-Oct-2015 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Reformat blank lines.
llvm-svn: 249284
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0b7d6c14 |
| 18-Sep-2015 |
Matthias Braun <matze@braunis.de> |
SelectionDAG: Introduce PersistentID to SDNode for assert builds.
This gives us more human readable numbers to identify nodes in debug dumps.
Before: 0x7fcbd9700160: ch = EntryToken
0x7fcbd985
SelectionDAG: Introduce PersistentID to SDNode for assert builds.
This gives us more human readable numbers to identify nodes in debug dumps.
Before: 0x7fcbd9700160: ch = EntryToken
0x7fcbd985c7c8: i64 = Register %RAX
...
0x7fcbd9700160: <multiple use> 0x7fcbd985c578: i64,ch = MOV64rm 0x7fcbd985c6a0, 0x7fcbd985cc68, 0x7fcbd985c200, 0x7fcbd985cd90, 0x7fcbd985ceb8, 0x7fcbd9700160<Mem:LD8[@foo]> [ORD=2]
0x7fcbd985c8f0: ch,glue = CopyToReg 0x7fcbd9700160, 0x7fcbd985c7c8, 0x7fcbd985c578 [ORD=3]
0x7fcbd985c7c8: <multiple use> 0x7fcbd985c8f0: <multiple use> 0x7fcbd985c8f0: <multiple use> 0x7fcbd985ca18: ch = RETQ 0x7fcbd985c7c8, 0x7fcbd985c8f0, 0x7fcbd985c8f0:1 [ORD=3]
Now: t0: ch = EntryToken
t5: i64 = Register %RAX
...
t0: <multiple use> t3: i64,ch = MOV64rm t10, t12, t11, t13, t14, t0<Mem:LD8[@foo]> [ORD=2]
t6: ch,glue = CopyToReg t0, t5, t3 [ORD=3]
t5: <multiple use> t6: <multiple use> t6: <multiple use> t7: ch = RETQ t5, t6, t6:1 [ORD=3]
Differential Revision: http://reviews.llvm.org/D12564
llvm-svn: 248010
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a260701b |
| 16-Sep-2015 |
Sanjay Patel <spatel@rotateright.com> |
propagate fast-math-flags on DAG nodes
After D10403, we had FMF in the DAG but disabled by default. Nick reported no crashing errors after some stress testing, so I enabled them at r243687. However
propagate fast-math-flags on DAG nodes
After D10403, we had FMF in the DAG but disabled by default. Nick reported no crashing errors after some stress testing, so I enabled them at r243687. However, Escha soon notified us of a bug not covered by any in-tree regression tests: if we don't propagate the flags, we may fail to CSE DAG nodes because differing FMF causes them to not match. There is one test case in this patch to prove that point.
This patch hopes to fix or leave a 'TODO' for all of the in-tree places where we create nodes that are FMF-capable. I did this by putting an assert in SelectionDAG.getNode() to find any FMF-capable node that was being created without FMF ( D11807 ). I then ran all regression tests and test-suite and confirmed that everything passes.
This patch exposes remaining work to get DAG FMF to be fully functional: (1) add the flags to non-binary nodes such as FCMP, FMA and FNEG; (2) add the flags to intrinsics; (3) use the flags as conditions for transforms rather than the current global settings.
Differential Revision: http://reviews.llvm.org/D12095
llvm-svn: 247815
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5cf3a029 |
| 10-Sep-2015 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added isUndef() interface for SDNode
Differential Revision: http://reviews.llvm.org/D12720
llvm-svn: 247246
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Revision tags: llvmorg-3.7.0, llvmorg-3.7.0-rc4, llvmorg-3.7.0-rc3, studio-1.4, llvmorg-3.7.0-rc2, llvmorg-3.7.0-rc1 |
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8c20b4eb |
| 14-Jul-2015 |
Pete Cooper <peter_cooper@apple.com> |
Move SDNode::IROrder in to padding to save space. NFC.
There was a 32-bit padding gap between 'unsigned short NumOperands, NumValues;' and 'DebugLoc debugLoc. Move 'unsigned IROrder' in to that ga
Move SDNode::IROrder in to padding to save space. NFC.
There was a 32-bit padding gap between 'unsigned short NumOperands, NumValues;' and 'DebugLoc debugLoc. Move 'unsigned IROrder' in to that gap.
This trims the size of SDNode's from 76 bytes (really 80 due to alignment) to 72 bytes.
llvm-svn: 242211
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06e249e7 |
| 14-Jul-2015 |
Pete Cooper <peter_cooper@apple.com> |
Constify parameters in SelectionDAG methods. NFC
llvm-svn: 242210
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9271ccc3 |
| 26-Jun-2015 |
Pete Cooper <peter_cooper@apple.com> |
Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.
llvm-svn: 240817
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3af9a25b |
| 26-Jun-2015 |
Pete Cooper <peter_cooper@apple.com> |
Add op_values() to iterate over the SDValue operands of an SDNode.
SDNode already had ops() which would iterate over the operands and return SDUse*. This version instead gets the SDValue's out of t
Add op_values() to iterate over the SDValue operands of an SDNode.
SDNode already had ops() which would iterate over the operands and return SDUse*. This version instead gets the SDValue's out of the SDUse's so that we can use foreach in more places.
Reviewed by David Blaikie.
llvm-svn: 240805
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Revision tags: llvmorg-3.6.2, llvmorg-3.6.2-rc1 |
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f00654e3 |
| 23-Jun-2015 |
Alexander Kornienko <alexfh@google.com> |
Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)
Apparently, the style needs to be agreed upon first.
llvm-svn: 240390
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36b718fc |
| 22-Jun-2015 |
Rafael Espindola <rafael.espindola@gmail.com> |
Avoid a Symbol -> Name -> Symbol conversion.
Before this we were producing a TargetExternalSymbol from a MCSymbol. That meant extracting the symbol name and fetching the symbol again down the pipeli
Avoid a Symbol -> Name -> Symbol conversion.
Before this we were producing a TargetExternalSymbol from a MCSymbol. That meant extracting the symbol name and fetching the symbol again down the pipeline.
This patch adds a DAG.getMCSymbol that lets the MCSymbol pass unchanged on the DAG.
Doing so removes the need for MO_NOPREFIX and fixes the root cause of pr23900, allowing r240130 to be committed again.
llvm-svn: 240300
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70bc5f13 |
| 19-Jun-2015 |
Alexander Kornienko <alexfh@google.com> |
Fixed/added namespace ending comments using clang-tidy. NFC
The patch is generated using this command:
tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-c
Fixed/added namespace ending comments using clang-tidy. NFC
The patch is generated using this command:
tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/
Thanks to Eugene Kosov for the original patch!
llvm-svn: 240137
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f134048b |
| 16-Jun-2015 |
Sanjay Patel <spatel@rotateright.com> |
propagate IR-level fast-math-flags to DAG nodes, disabled by default
This is an updated version of the patch that was checked in at: http://reviews.llvm.org/rL237046
but subsequently reverted becau
propagate IR-level fast-math-flags to DAG nodes, disabled by default
This is an updated version of the patch that was checked in at: http://reviews.llvm.org/rL237046
but subsequently reverted because it exposed a bug in the DAG Combiner: http://reviews.llvm.org/D9893
This time, there's an enablement flag ("EnableFMFInDAG") around the code in SelectionDAGBuilder where we copy the set of FP optimization flags from IR instructions to DAG nodes. So, in theory, there should be no functional change from this patch as-is, but it will allow testing with the added functionality to proceed via "-enable-fmf-dag" passed to llc.
This patch adds the minimum plumbing necessary to use IR-level fast-math-flags (FMF) in the backend without actually using them for anything yet. This is a follow-on to: http://reviews.llvm.org/rL235997
Differential Revision: http://reviews.llvm.org/D10403
llvm-svn: 239828
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