History log of /llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h (Results 176 – 200 of 866)
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Revision tags: llvmorg-6.0.1-rc1
# 2fa14362 29-Mar-2018 Craig Topper <craig.topper@intel.com>

[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.

Currently EVT is in the IR layer only because of Function.cpp needing a very small piece of the functionality

[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.

Currently EVT is in the IR layer only because of Function.cpp needing a very small piece of the functionality of EVT::getEVTString(). The rest of EVT is used in codegen making CodeGen a better place for it.

The previous code converted a Type* to EVT and then called getEVTString. This was only expected to handle the primitive types from Type*. Since there only a few primitive types, we can just print them as strings directly.

Differential Revision: https://reviews.llvm.org/D45017

llvm-svn: 328806

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Revision tags: llvmorg-5.0.2, llvmorg-5.0.2-rc2
# 36a0f226 23-Mar-2018 David Blaikie <dblaikie@gmail.com>

Fix layering by moving ValueTypes.h from CodeGen to IR

ValueTypes.h is implemented in IR already.

llvm-svn: 328397


# 13e77db2 23-Mar-2018 David Blaikie <dblaikie@gmail.com>

Fix layering of MachineValueType.h by moving it from CodeGen to Support

This is used by llvm tblgen as well as by LLVM Targets, so the only
common place is Support for now. (maybe we need another ta

Fix layering of MachineValueType.h by moving it from CodeGen to Support

This is used by llvm tblgen as well as by LLVM Targets, so the only
common place is Support for now. (maybe we need another target for these
sorts of things - but for now I'm at least making them correct & we can
make them better if/when people have strong feelings)

llvm-svn: 328395

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# 3264c1bd 19-Mar-2018 Nirav Dave <niravd@google.com>

[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"

Reland ISel cycle checking improvements after simplifying node id
invariant traversal and correcting typo.

llvm-svn: 327898


# f7fdfb3f 18-Mar-2018 Craig Topper <craig.topper@intel.com>

[SelectionDAG] Don't default the SelectionDAG* parameter to SDValue::dump to nullptr. Use two different signatures instead.

This matches what we do in SDNode.

This should allow SDValue::dump to be

[SelectionDAG] Don't default the SelectionDAG* parameter to SDValue::dump to nullptr. Use two different signatures instead.

This matches what we do in SDNode.

This should allow SDValue::dump to be used in the debugger without getting an error if you don't pass an argument.

llvm-svn: 327811

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# 5f0ab71b 17-Mar-2018 Nirav Dave <niravd@google.com>

Revert "[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172""

as it times out building test-suite on PPC.

llvm-svn: 327778


# 982d3a56 17-Mar-2018 Nirav Dave <niravd@google.com>

[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"

Reland ISel cycle checking improvements after simplifying and reducing
node id invariant traversal.

llvm-svn: 327777


Revision tags: llvmorg-5.0.2-rc1
# c683966c 14-Mar-2018 Alexander Timofeev <Alexander.Timofeev@amd.com>

[AMDGPU] Fix for DAGCombiner infinite loop in OCLtst

Differential revision: https://reviews.llvm.org/D44417

llvm-svn: 327488


# 042678bd 10-Mar-2018 Nirav Dave <niravd@google.com>

Revert: r327172 "Correct load-op-store cycle detection analysis"
r327171 "Improve Dependency analysis when doing multi-node Instruction Selection"
r328170 "[DAG] Enforce stricter Node

Revert: r327172 "Correct load-op-store cycle detection analysis"
r327171 "Improve Dependency analysis when doing multi-node Instruction Selection"
r328170 "[DAG] Enforce stricter NodeId invariant during Instruction selection"

Reverting patch as NodeId invariant change is causing pathological
increases in compile time on PPC

llvm-svn: 327197

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# d668f69e 09-Mar-2018 Nirav Dave <niravd@google.com>

Improve Dependency analysis when doing multi-node Instruction Selection

Relanding after fixing NodeId Invariant.

Cleanup cycle/validity checks in ISel (IsLegalToFold,
HandleMergeInputChains) and X8

Improve Dependency analysis when doing multi-node Instruction Selection

Relanding after fixing NodeId Invariant.

Cleanup cycle/validity checks in ISel (IsLegalToFold,
HandleMergeInputChains) and X86 (isFusableLoadOpStore). Now do a full
search for cycles / dependencies pruning the search when topological
property of NodeId allows.

As part of this propogate the NodeId-based cutoffs to narrow
hasPreprocessorHelper searches.

Reviewers: craig.topper, bogner

Subscribers: llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D41293

llvm-svn: 327171

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# 775f07d1 09-Mar-2018 Nirav Dave <niravd@google.com>

Make early exit hasPredecessorHelper return true. NFCI.

All uses conservatively assume in early exit case that it will be a
predecessor. Changing default removes checking code in all uses.

llvm-svn

Make early exit hasPredecessorHelper return true. NFCI.

All uses conservatively assume in early exit case that it will be a
predecessor. Changing default removes checking code in all uses.

llvm-svn: 327169

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# 2e5eecee 05-Mar-2018 Alexander Timofeev <Alexander.Timofeev@amd.com>

Pass Divergence Analysis data to Selection DAG to drive divergence
dependent instruction selection.

Differential revision: https://reviews.llvm.org/D35267

llvm-svn: 326703


Revision tags: llvmorg-6.0.0, llvmorg-6.0.0-rc3
# be72fe1f 22-Feb-2018 Simon Pilgrim <llvm-dev@redking.me.uk>

[SelectionDAG] Move matchUnaryPredicate/matchBinaryPredicate into SelectionDAGNodes.h

This allows us to improve vector constant matching in more DAG code (backends, TargetLowering etc.).

Differenti

[SelectionDAG] Move matchUnaryPredicate/matchBinaryPredicate into SelectionDAGNodes.h

This allows us to improve vector constant matching in more DAG code (backends, TargetLowering etc.).

Differential Revision: https://reviews.llvm.org/D43466

llvm-svn: 325815

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# a1d6107b 17-Feb-2018 Chandler Carruth <chandlerc@gmail.com>

[DAG, X86] Revert r324797, r324491, and r324359.

Sadly, r324359 caused at least PR36312. There is a patch out for review
but it seems to be taking a bit and we've already had these crashers in
tree

[DAG, X86] Revert r324797, r324491, and r324359.

Sadly, r324359 caused at least PR36312. There is a patch out for review
but it seems to be taking a bit and we've already had these crashers in
tree for too long. We're hitting this PR in real code now and are
blocked on shipping new compilers as a consequence so I'm reverting us
back to green.

Sorry for the churn due to the stacked changes that I had to revert. =/

llvm-svn: 325420

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# 02f08c9d 12-Feb-2018 Oliver Stannard <oliver.stannard@arm.com>

[AArch64] Improve v8.1-A code-gen for atomic load-and

Armv8.1-A added an atomic load-clear instruction (which performs bitwise
and with the complement of it's operand), but not a load-and
instructio

[AArch64] Improve v8.1-A code-gen for atomic load-and

Armv8.1-A added an atomic load-clear instruction (which performs bitwise
and with the complement of it's operand), but not a load-and
instruction. Our current code-generation for atomic load-and always
inserts an MVN instruction to invert its argument, even if it could be
folded into a constant or another instruction.

This adds lowering early in selection DAG to convert a load-and
operation into an xor with -1 and a load-clear, allowing the normal DAG
optimisations to work on it.

To do this, I've had to add a new ISD opcode, ATOMIC_LOAD_CLR. I don't
see any easy way to do this with an AArch64-specific ISD node, because
the code-generation for atomic operations assumes the SDNodes are of
type AtomicSDNode.

I've left the old tablegen patterns in because they are still needed for
global isel.

Differential revision: https://reviews.llvm.org/D42478

llvm-svn: 324908

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# c8c9d4fe 10-Feb-2018 Nirav Dave <niravd@google.com>

[DAG] Make early exit hasPredecessorHelper return true. NFCI.

All uses conservatively assume in early exit case that it will be a
predecessor. Changing default removes checking code in all uses.

ll

[DAG] Make early exit hasPredecessorHelper return true. NFCI.

All uses conservatively assume in early exit case that it will be a
predecessor. Changing default removes checking code in all uses.

llvm-svn: 324797

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Revision tags: llvmorg-6.0.0-rc2
# 27721e86 06-Feb-2018 Nirav Dave <niravd@google.com>

[DAG, X86] Improve Dependency analysis when doing multi-node
Instruction Selection

Cleanup cycle/validity checks in ISel (IsLegalToFold,
HandleMergeInputChains) and X86 (isFusableLoadOpStore). Now d

[DAG, X86] Improve Dependency analysis when doing multi-node
Instruction Selection

Cleanup cycle/validity checks in ISel (IsLegalToFold,
HandleMergeInputChains) and X86 (isFusableLoadOpStore). Now do a full
search for cycles / dependencies pruning the search when topological
property of NodeId allows.

As part of this propogate the NodeId-based cutoffs to narrow
hasPreprocessorHelper searches.

Reviewers: craig.topper, bogner

Subscribers: llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D41293

llvm-svn: 324359

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Revision tags: llvmorg-6.0.0-rc1
# af4eb172 10-Jan-2018 Craig Topper <craig.topper@intel.com>

[SelectionDAG][X86] Explicitly store the scale in the gather/scatter ISD nodes

Currently we infer the scale at isel time by analyzing whether the base is a constant 0 or not. If it is we assume scal

[SelectionDAG][X86] Explicitly store the scale in the gather/scatter ISD nodes

Currently we infer the scale at isel time by analyzing whether the base is a constant 0 or not. If it is we assume scale is 1, else we take it from the element size of the pass thru or stored value. This seems a little weird and I think it makes more sense to make it explicit in the DAG rather than doing tricky things in the backend.

Most of this patch is just making sure we copy the scale around everywhere.

Differential Revision: https://reviews.llvm.org/D40055

llvm-svn: 322210

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# 3257e44c 20-Dec-2017 Krzysztof Parzyszek <kparzysz@codeaurora.org>

Add optional SelectionDAG* parameter to SValue::dump and SDValue::dumpr

These functions simply call their counterparts in the associated SDNode,
which do take an optional SelectionDAG. This change m

Add optional SelectionDAG* parameter to SValue::dump and SDValue::dumpr

These functions simply call their counterparts in the associated SDNode,
which do take an optional SelectionDAG. This change makes the legalization
debug trace a little easier to read, since target-specific nodes will
now have their names shown instead of "Unknown node #123".

llvm-svn: 321180

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Revision tags: llvmorg-5.0.1, llvmorg-5.0.1-rc3, llvmorg-5.0.1-rc2
# 433e8d3e 16-Nov-2017 Guozhi Wei <carrot@google.com>

[PPC] Change i32 constant in store instruction to i64

This patch changes all i32 constant in store instruction to i64 with truncation, to increase the chance that the referenced constant can be shar

[PPC] Change i32 constant in store instruction to i64

This patch changes all i32 constant in store instruction to i64 with truncation, to increase the chance that the referenced constant can be shared with other i64 constant.

Differential Revision: https://reviews.llvm.org/D39352

llvm-svn: 318436

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# cfd51067 08-Nov-2017 Craig Topper <craig.topper@intel.com>

[X86] X86MaskedGatherSDNode shouldn't inherit from MaskedGatherScatterSDNode

The classof implementation in MaskedGatherScatterSDNode doesn't consider X86MaskedGatherSDNode so its misleading.

llvm-s

[X86] X86MaskedGatherSDNode shouldn't inherit from MaskedGatherScatterSDNode

The classof implementation in MaskedGatherScatterSDNode doesn't consider X86MaskedGatherSDNode so its misleading.

llvm-svn: 317733

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Revision tags: llvmorg-5.0.1-rc1
# 649c5857 13-Oct-2017 Daniel Sanders <daniel_l_sanders@apple.com>

[aarch64] Support APInt and APFloat in ImmLeaf subclasses and make AArch64 use them.

Summary:
The purpose of this patch is to expose more information about ImmLeaf-like
PatLeaf's so that GlobalISel

[aarch64] Support APInt and APFloat in ImmLeaf subclasses and make AArch64 use them.

Summary:
The purpose of this patch is to expose more information about ImmLeaf-like
PatLeaf's so that GlobalISel can learn to import them. Previously, ImmLeaf
could only be used to test int64_t's produced by sign-extending an APInt.
Other tests on immediates had to use the generic PatLeaf and extract the
constant using C++.

With this patch, tablegen will know how to generate predicates for APInt,
and APFloat. This will allow it to 'do the right thing' for both SelectionDAG
and GlobalISel which require different methods of extracting the immediate
from the IR.

This is NFC for SelectionDAG since the new code is equivalent to the
previous code. It's also NFC for FastISel because FastIselShouldIgnore is 1
for the ImmLeaf subclasses. Enabling FastIselShouldIgnore == 0 for these new
subclasses will require a significant re-factor of FastISel.

For GlobalISel, it's currently NFC because the relevant code to import the
affected rules is not yet present. This will be added in a later patch.

Depends on D36086

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Reviewed By: qcolombet

Subscribers: bjope, aemerson, rengolin, javed.absar, igorb, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D36534

llvm-svn: 315747

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# 5bc10ede 25-Sep-2017 Craig Topper <craig.topper@intel.com>

[SelectionDAG] Teach simplifyDemandedBits to handle shifts by constant splat vectors

This teach simplifyDemandedBits to handle constant splat vector shifts.

This required changing some uses of getZ

[SelectionDAG] Teach simplifyDemandedBits to handle shifts by constant splat vectors

This teach simplifyDemandedBits to handle constant splat vector shifts.

This required changing some uses of getZExtValue to getLimitedValue since we can't rely on legalization using getShiftAmountTy for the shift amount.

I believe there may have been a bug in the ((X << C1) >>u ShAmt) handling where we didn't check if the inner shift was too large. I've fixed that here.

I had to add new patterns to ARM because the zext/sext the patterns were trying to look for got turned into an any_extend with this patch. Happy to split that out too, but not sure how to test without this change.

Differential Revision: https://reviews.llvm.org/D37665

llvm-svn: 314139

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# e33c94f1 05-Sep-2017 Reid Kleckner <rnk@google.com>

Add llvm.codeview.annotation to implement MSVC __annotation

Summary:
This intrinsic represents a label with a list of associated metadata
strings. It is modelled as reading and writing inaccessible

Add llvm.codeview.annotation to implement MSVC __annotation

Summary:
This intrinsic represents a label with a list of associated metadata
strings. It is modelled as reading and writing inaccessible memory so
that it won't be removed as dead code. I think the intention is that the
annotation strings should appear at most once in the debug info, so I
marked it noduplicate. We are allowed to inline code with annotations as
long as we strip the annotation, but that can be done later.

Reviewers: majnemer

Subscribers: eraman, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D36904

llvm-svn: 312569

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Revision tags: llvmorg-5.0.0, llvmorg-5.0.0-rc5, llvmorg-5.0.0-rc4
# e7becd7e 29-Aug-2017 Hans Wennborg <hans@hanshq.net>

[DAG] Bound loop dependence check in merge optimization.

The loop dependence check looks for dependencies between store merge
candidates not captured by the chain sub-DAG doing a check of
predecesso

[DAG] Bound loop dependence check in merge optimization.

The loop dependence check looks for dependencies between store merge
candidates not captured by the chain sub-DAG doing a check of
predecessors which may be very large. Conservatively bound number of
nodes checked for compilation time. (Resolves PR34326).

Landing on behalf of Nirav Dave to unblock the 5.0.0 release.

Differential Revision: https://reviews.llvm.org/D37220

llvm-svn: 312022

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