| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUArgumentUsageInfo.cpp | 154 = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3); in fixedABILayout()
155 AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5); in fixedABILayout()
156 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7); in fixedABILayout()
160 AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9); in fixedABILayout()
161 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11); in fixedABILayout()
164 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12); in fixedABILayout()
165 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13); in fixedABILayout()
166 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14); in fixedABILayout()
167 AI.LDSKernelId = ArgDescriptor::createRegister(AMDGPU::SGPR15); in fixedABILayout()
170 AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask); in fixedABILayout()
[all …]
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| H A D | SIMachineFunctionInfo.cpp | 100 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
183 ArgDescriptor::createRegister(AMDGPU::SGPR5); in SIMachineFunctionInfo()
223 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
230 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
237 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
245 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
252 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
259 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
266 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addImplicitBufferPtr()
273 ArgInfo.LDSKernelId = ArgDescriptor::createRegister(getNextUserSGPR()); in addLDSKernelId()
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| H A D | SIMachineFunctionInfo.h | 697 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
703 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
709 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
715 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
735 = ArgDescriptor::createRegister(getNextSystemSGPR());
741 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
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| H A D | AMDGPUArgumentUsageInfo.h | 44 static constexpr ArgDescriptor createRegister(Register Reg,
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| H A D | AMDGPUTargetMachine.cpp | 1524 Arg = ArgDescriptor::createRegister(Reg); in parseMachineFunctionInfo()
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| H A D | SIISelLowering.cpp | 1933 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask)); in allocateSpecialEntryInputVGPRs()
1939 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
1946 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
1953 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
1960 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
1990 return ArgDescriptor::createRegister(Reg, Mask); in allocateVGPR32Input()
2007 return ArgDescriptor::createRegister(Reg); in allocateSGPR32InputImpl()
2069 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask)); in allocateSpecialInputVGPRsFixed()
2070 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg, Mask << 10)); in allocateSpecialInputVGPRsFixed()
2071 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg, Mask << 20)); in allocateSpecialInputVGPRsFixed()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfExpression.cpp | 104 DwarfRegs.push_back(Register::createRegister(-1, nullptr)); in addMachineReg()
114 DwarfRegs.push_back(Register::createRegister(Reg, nullptr)); in addMachineReg()
126 DwarfRegs.push_back(Register::createRegister(Reg, "super-register")); in addMachineReg()
166 DwarfRegs.push_back(Register::createRegister(Reg, "sub-register")); in addMachineReg()
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| H A D | DwarfExpression.h | 114 static Register createRegister(int RegNo, const char *Comment) { in createRegister() function
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | CFIInstrInserter.cpp | 376 MCCFIInstruction::createRegister(nullptr, Reg, *RO.Reg)); in insertCFIInstrs()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/ |
| H A D | SparcFrameLowering.cpp | 168 MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA)); in emitPrologue()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/MC/ |
| H A D | MCDwarf.h | 586 static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, in createRegister() function
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| /openbsd-src/gnu/llvm/llvm/lib/MC/ |
| H A D | MCStreamer.cpp | 661 MCCFIInstruction::createRegister(Label, Register1, Register2); in emitCFIRegister()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 1212 unsigned CFIRegister = MF.addFrameInst(MCCFIInstruction::createRegister( in emitPrologue()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 2548 MF.addFrameInst(MCCFIInstruction::createRegister(nullptr, Reg, Reg2)); in parseCFIOperand()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 6527 MCCFIInstruction::createRegister(nullptr, DwarfLR, DwarfReg)); in emitCFIForLRSaveToReg()
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