| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 50 MVT RegisterVT = TLI.getRegisterType(Ctx, VT); in computeLegalValueVTs() local
52 ValueVTs.push_back(RegisterVT); in computeLegalValueVTs()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1101 MVT &RegisterVT, in getVectorTypeBreakdownMVT() argument
1146 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1486 MVT RegisterVT; in computeRegisterProperties() local
1489 NumIntermediates, RegisterVT, this); in computeRegisterProperties()
1493 RegisterTypeForVT[i] = RegisterVT; in computeRegisterProperties()
1555 MVT &RegisterVT) const { in getVectorTypeBreakdown()
1569 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1600 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1627 RegisterVT = DestVT; in getVectorTypeBreakdown()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 418 std::optional<MVT> RegisterVT) const override { in getNumRegisters() argument
420 if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped) in getNumRegisters()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 385 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
389 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
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| H A D | SelectionDAGBuilder.cpp | 335 MVT RegisterVT; in getCopyFromPartsVector() local
342 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
346 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
351 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyFromPartsVector()
352 assert(RegisterVT.getSizeInBits() == in getCopyFromPartsVector()
717 MVT RegisterVT; in getCopyToPartsVector() local
723 RegisterVT); in getCopyToPartsVector()
727 NumIntermediates, RegisterVT); in getCopyToPartsVector()
732 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyToPartsVector()
821 MVT RegisterVT = in RegsForValue() local
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| H A D | FastISel.cpp | 1006 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
1010 MyFlags.VT = RegisterVT; in lowerCallTo()
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| H A D | SelectionDAG.cpp | 2330 MVT RegisterVT; in getReducedAlign() local
2333 NumIntermediates, RegisterVT); in getReducedAlign()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1033 MVT &RegisterVT) const;
1040 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
1042 RegisterVT); in getVectorTypeBreakdownForCallingConv()
1559 MVT RegisterVT; in getRegisterType() local
1562 NumIntermediates, RegisterVT); in getRegisterType()
1563 return RegisterVT; in getRegisterType()
1584 std::optional<MVT> RegisterVT = std::nullopt) const {
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1062 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); in analyzeFormalArgumentsCompute() local
1070 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1074 } else if (ArgVT.isVector() && RegisterVT.isVector() && in analyzeFormalArgumentsCompute()
1075 ArgVT.getScalarType() == RegisterVT.getScalarType()) { in analyzeFormalArgumentsCompute()
1076 assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements()); in analyzeFormalArgumentsCompute()
1080 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1088 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1092 if (RegisterVT.isInteger()) { in analyzeFormalArgumentsCompute()
1094 } else if (RegisterVT.isVector()) { in analyzeFormalArgumentsCompute()
1095 assert(!RegisterVT.getScalarType().isFloatingPoint()); in analyzeFormalArgumentsCompute()
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| H A D | SIISelLowering.h | 45 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | SIISelLowering.cpp | 899 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
909 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
912 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16; in getVectorTypeBreakdownForCallingConv()
913 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
920 RegisterVT = ScalarVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
921 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
928 RegisterVT = MVT::i16; in getVectorTypeBreakdownForCallingConv()
936 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
943 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
944 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 306 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | MipsISelLowering.cpp | 119 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
121 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); in getVectorTypeBreakdownForCallingConv()
122 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
124 VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits() in getVectorTypeBreakdownForCallingConv()
126 : divideCeil(VT.getSizeInBits(), RegisterVT.getSizeInBits()); in getVectorTypeBreakdownForCallingConv()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1509 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | X86ISelLowering.cpp | 2516 MVT RegisterVT; in getRegisterTypeForCallingConv() local
2518 std::tie(RegisterVT, NumRegisters) = in getRegisterTypeForCallingConv()
2520 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getRegisterTypeForCallingConv()
2521 return RegisterVT; in getRegisterTypeForCallingConv()
2547 MVT RegisterVT; in getNumRegistersForCallingConv() local
2549 std::tie(RegisterVT, NumRegisters) = in getNumRegistersForCallingConv()
2551 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getNumRegistersForCallingConv()
2577 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
2584 RegisterVT = MVT::i8; in getVectorTypeBreakdownForCallingConv()
2593 RegisterVT = MVT::v32i8; in getVectorTypeBreakdownForCallingConv()
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