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Searched refs:Cond (Results 1 – 25 of 359) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Transforms/Scalar/
H A DLoopBoundSplit.cpp52 ConditionInfo &Cond, const Loop &L) { in analyzeICmp() argument
53 Cond.ICmp = ICmp; in analyzeICmp()
54 if (match(ICmp, m_ICmp(Cond.Pred, m_Value(Cond.AddRecValue), in analyzeICmp()
55 m_Value(Cond.BoundValue)))) { in analyzeICmp()
56 const SCEV *AddRecSCEV = SE.getSCEV(Cond.AddRecValue); in analyzeICmp()
57 const SCEV *BoundSCEV = SE.getSCEV(Cond.BoundValue); in analyzeICmp()
62 std::swap(Cond.AddRecValue, Cond.BoundValue); in analyzeICmp()
64 Cond.Pred = ICmpInst::getSwappedPredicate(Cond.Pred); in analyzeICmp()
67 Cond.AddRecSCEV = dyn_cast<SCEVAddRecExpr>(AddRecSCEV); in analyzeICmp()
68 Cond.BoundSCEV = BoundSCEV; in analyzeICmp()
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/openbsd-src/gnu/llvm/clang/lib/StaticAnalyzer/Core/
H A DSimpleConstraintManager.cpp27 DefinedSVal Cond, in assumeInternal() argument
30 if (std::optional<Loc> LV = Cond.getAs<Loc>()) { in assumeInternal()
39 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>(); in assumeInternal()
42 return assume(State, Cond.castAs<NonLoc>(), Assumption); in assumeInternal()
46 NonLoc Cond, bool Assumption) { in assume() argument
47 State = assumeAux(State, Cond, Assumption); in assume()
49 return EE->processAssume(State, Cond, Assumption); in assume()
54 NonLoc Cond, in assumeAux() argument
59 if (!canReasonAbout(Cond)) { in assumeAux()
61 SymbolRef Sym = Cond.getAsSymbol(); in assumeAux()
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/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp92 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
110 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
111 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
118 Cond.push_back(MachineOperand::CreateImm(false)); in analyzeBranch()
119 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
161 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
164 if (Cond.empty()) { in insertBranch()
172 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in insertBranch()
174 if (Cond[0].getImm()) in insertBranch()
175 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); in insertBranch()
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H A DWebAssemblyLowerBrUnless.cpp70 Register Cond = MI.getOperand(1).getReg(); in runOnMachineFunction() local
74 if (MFI.isVRegStackified(Cond)) { in runOnMachineFunction()
75 assert(MRI.hasOneDef(Cond)); in runOnMachineFunction()
76 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction()
177 Cond = Def->getOperand(1).getReg(); in runOnMachineFunction()
192 .addReg(Cond); in runOnMachineFunction()
194 Cond = Tmp; in runOnMachineFunction()
203 .addReg(Cond); in runOnMachineFunction()
H A DWebAssemblyFixBrTableDefaults.cpp101 SmallVector<MachineOperand, 2> Cond; in fixBrTableDefault() local
103 bool Analyzed = !TII.analyzeBranch(*HeaderMBB, TBB, FBB, Cond); in fixBrTableDefault()
118 assert(Cond.size() == 2 && Cond[1].isReg() && "Unexpected condition info"); in fixBrTableDefault()
127 auto *RangeCheck = MRI.getVRegDef(Cond[1].getReg()); in fixBrTableDefault()
/openbsd-src/gnu/llvm/clang/lib/Analysis/FlowSensitive/
H A DTypeErasedDataflowAnalysis.cpp104 auto *Cond = S->getCond(); in VisitIfStmt() local
105 assert(Cond != nullptr); in VisitIfStmt()
106 return extendFlowCondition(*Cond); in VisitIfStmt()
110 auto *Cond = S->getCond(); in VisitWhileStmt() local
111 assert(Cond != nullptr); in VisitWhileStmt()
112 return extendFlowCondition(*Cond); in VisitWhileStmt()
116 auto *Cond = S->getCond(); in VisitDoStmt() local
117 assert(Cond != nullptr); in VisitDoStmt()
118 return extendFlowCondition(*Cond); in VisitDoStmt()
122 auto *Cond = S->getCond(); in VisitForStmt() local
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/openbsd-src/gnu/llvm/llvm/lib/Transforms/Utils/
H A DLibCallsShrinkWrap.cpp96 void shrinkWrapCI(CallInst *CI, Value *Cond);
139 Value *Cond = nullptr; in performCallDomainErrorOnly() local
150 Cond = createOrCond(CI, CmpInst::FCMP_OLT, -1.0f, CmpInst::FCMP_OGT, 1.0f); in performCallDomainErrorOnly()
161 Cond = createOrCond(CI, CmpInst::FCMP_OEQ, INFINITY, CmpInst::FCMP_OEQ, in performCallDomainErrorOnly()
170 Cond = createCond(CI, CmpInst::FCMP_OLT, 1.0f); in performCallDomainErrorOnly()
178 Cond = createCond(CI, CmpInst::FCMP_OLT, 0.0f); in performCallDomainErrorOnly()
184 shrinkWrapCI(CI, Cond); in performCallDomainErrorOnly()
191 Value *Cond = nullptr; in performCallRangeErrorOnly() local
209 Cond = generateTwoRangeCond(CI, Func); in performCallRangeErrorOnly()
216 Cond = generateOneRangeCond(CI, Func); in performCallRangeErrorOnly()
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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVRedundantCopyElimination.cpp75 const SmallVectorImpl<MachineOperand> &Cond, in guaranteesZeroRegInBlock() argument
77 assert(Cond.size() == 3 && "Unexpected number of operands"); in guaranteesZeroRegInBlock()
79 auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm()); in guaranteesZeroRegInBlock()
80 if (CC == RISCVCC::COND_EQ && Cond[2].getReg() == RISCV::X0 && TBB == &MBB) in guaranteesZeroRegInBlock()
82 if (CC == RISCVCC::COND_NE && Cond[2].getReg() == RISCV::X0 && TBB != &MBB) in guaranteesZeroRegInBlock()
99 SmallVector<MachineOperand, 3> Cond; in optimizeBlock() local
100 if (TII->analyzeBranch(*PredMBB, TBB, FBB, Cond, /*AllowModify*/ false) || in optimizeBlock()
101 Cond.empty()) in optimizeBlock()
105 if (!guaranteesZeroRegInBlock(MBB, Cond, TBB)) in optimizeBlock()
108 Register TargetReg = Cond[1].getReg(); in optimizeBlock()
/openbsd-src/gnu/llvm/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp133 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
134 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in reverseBranchCondition()
136 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
160 Cond[0].setImm(CC); in reverseBranchCondition()
167 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
201 Cond.clear(); in analyzeBranch()
225 if (Cond.empty()) { in analyzeBranch()
228 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
234 assert(Cond.size() == 1); in analyzeBranch()
242 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
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/openbsd-src/gnu/llvm/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp192 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
220 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
221 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
241 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
242 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
274 ArrayRef<MachineOperand> Cond, in insertBranch() argument
279 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
284 if (Cond.empty()) { in insertBranch()
289 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
290 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp173 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
202 if (!Cond.empty()) in analyzeBranch()
208 Cond.push_back(I->getOperand(1)); in analyzeBranch()
209 Cond.push_back(I->getOperand(2)); in analyzeBranch()
210 Cond.push_back(I->getOperand(3)); in analyzeBranch()
225 Cond.clear(); in analyzeBranch()
350 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
351 assert((Cond.size() == 3) && "Invalid ARC branch condition!"); in reverseBranchCondition()
352 Cond[2].setImm(getOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm())); in reverseBranchCondition()
372 ArrayRef<MachineOperand> Cond, in insertBranch() argument
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/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp200 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
207 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode())); in parseCondBranch()
209 Cond.push_back(LastInst.getOperand(i)); in parseCondBranch()
215 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
218 Cond.clear(); in analyzeBranch()
256 parseCondBranch(*I, TBB, Cond); in analyzeBranch()
263 parseCondBranch(*std::prev(I), TBB, Cond); in analyzeBranch()
330 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
336 assert(Cond.size() <= 3 && Cond.size() != 1 && in insertBranch()
340 if (Cond.empty()) { in insertBranch()
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/openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp98 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
116 Cond.push_back(LastInst.getOperand(0)); in analyzeBranch()
134 Cond.push_back(SecondLastInst.getOperand(0)); in analyzeBranch()
183 ArrayRef<MachineOperand> Cond, in insertBranch() argument
190 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
195 if (Cond.empty()) // Unconditional branch in insertBranch()
198 BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); in insertBranch()
203 BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); in insertBranch()
/openbsd-src/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1416 unsigned Cond = 0; in LowerXALUO() local
1423 Cond = M68k::COND_VS; in LowerXALUO()
1427 Cond = M68k::COND_CS; in LowerXALUO()
1431 Cond = M68k::COND_VS; in LowerXALUO()
1435 Cond = M68k::COND_CS; in LowerXALUO()
1443 DAG.getConstant(Cond, DL, MVT::i8), in LowerXALUO()
1467 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ; in getBitTestCondition() local
1469 DAG.getConstant(Cond, DL, MVT::i8), BTST); in getBitTestCondition()
2011 SDValue Cond = Op.getOperand(3); in LowerSETCCCARRY() local
2015 M68k::CondCode CC = TranslateIntegerM68kCC(cast<CondCodeSDNode>(Cond)->get()); in LowerSETCCCARRY()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp95 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
102 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
105 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
111 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
114 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in analyzeBranch()
121 ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
122 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
126 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
127 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
129 MIB.add(Cond[i]); in BuildCondBr()
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H A DMipsInstrInfo.h65 SmallVectorImpl<MachineOperand> &Cond,
72 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
81 SmallVectorImpl<MachineOperand> &Cond,
206 SmallVectorImpl<MachineOperand> &Cond) const;
209 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp102 const DebugLoc &TestLoc, X86::CondCode Cond);
105 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
740 X86::CondCode Cond = X86::getCondFromSETCC(MI); in collectCondsInRegs() local
741 if (Cond != X86::COND_INVALID && !MI.mayStore() && in collectCondsInRegs()
745 CondRegs[Cond] = MI.getOperand(0).getReg(); in collectCondsInRegs()
758 const DebugLoc &TestLoc, X86::CondCode Cond) { in promoteCondToReg() argument
761 TII->get(X86::SETCCr), Reg).addImm(Cond); in promoteCondToReg()
770 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs) { in getCondOrInverseInReg() argument
771 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg()
772 unsigned &InvCondReg = CondRegs[X86::GetOppositeBranchCondition(Cond)]; in getCondOrInverseInReg()
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H A DX86InstrCMovSetCC.td87 multiclass CMOV_SETCC_Aliases<string Cond, int CC> {
88 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
90 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
92 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
94 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
96 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
98 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
101 def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>;
102 def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>;
/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp262 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
300 Cond.clear(); in analyzeBranch()
324 if (Cond.empty()) { in analyzeBranch()
365 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
371 assert(Cond.size() == 1); in analyzeBranch()
380 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm(); in analyzeBranch()
395 ArrayRef<MachineOperand> Cond, in insertBranch() argument
402 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
405 if (Cond.empty()) { in insertBranch()
415 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
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/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFAdjustOpt.cpp242 auto *Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB() local
243 if (!Cond || B2->getFirstNonPHI() != Cond) in serializeICMPCrossBB()
245 Value *B2Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
246 auto Cond2Op = Cond->getPredicate(); in serializeICMPCrossBB()
252 Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB()
253 if (!Cond) in serializeICMPCrossBB()
255 Value *B1Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
256 auto Cond1Op = Cond->getPredicate(); in serializeICMPCrossBB()
277 PassThroughInfo Info(Cond, BI, 0); in serializeICMPCrossBB()
/openbsd-src/gnu/llvm/llvm/lib/Analysis/
H A DGuardUtils.cpp66 auto *Cond = BI->getCondition(); in parseWidenableBranch() local
67 if (!Cond->hasOneUse()) in parseWidenableBranch()
73 if (match(Cond, m_Intrinsic<Intrinsic::experimental_widenable_condition>())) { in parseWidenableBranch()
85 if (!match(Cond, m_And(m_Value(A), m_Value(B)))) in parseWidenableBranch()
87 auto *And = dyn_cast<Instruction>(Cond); in parseWidenableBranch()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUAsmUtils.h31 bool (*Cond)(T Context) = nullptr; member
40 bool (*Cond)(const MCSubtargetInfo &STI) = nullptr; member
52 return !Cond || Cond(STI); in isSupported()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIAnnotateControlFlow.cpp83 handleLoopCondition(Value *Cond, PHINode *Broken, llvm::Loop *L,
228 Value *Cond, PHINode *Broken, llvm::Loop *L, BranchInst *Term) { in handleLoopCondition() argument
229 if (Instruction *Inst = dyn_cast<Instruction>(Cond)) { in handleLoopCondition()
238 Value *Args[] = { Cond, Broken }; in handleLoopCondition()
243 if (isa<Constant>(Cond)) { in handleLoopCondition()
244 Instruction *Insert = Cond == BoolTrue ? in handleLoopCondition()
247 Value *Args[] = { Cond, Broken }; in handleLoopCondition()
251 if (isa<Argument>(Cond)) { in handleLoopCondition()
253 Value *Args[] = { Cond, Broken }; in handleLoopCondition()
273 Value *Cond = Term->getCondition(); in handleLoop() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp36 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
41 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode())); in parseCondBranch()
42 Cond.push_back(LastInst.getOperand(0)); in parseCondBranch()
48 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
51 Cond.clear(); in analyzeBranch()
97 parseCondBranch(*I, TBB, Cond); in analyzeBranch()
104 parseCondBranch(*std::prev(I), TBB, Cond); in analyzeBranch()
156 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
162 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
166 if (Cond.empty()) { in insertBranch()
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/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp138 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
139 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm())); in parseCondBranch()
140 Cond.push_back(LastInst->getOperand(1)); in parseCondBranch()
141 Cond.push_back(LastInst->getOperand(2)); in parseCondBranch()
147 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
168 parseCondBranch(LastInst, TBB, Cond); in analyzeBranch()
201 parseCondBranch(SecondLastInst, TBB, Cond); in analyzeBranch()
229 ArrayRef<MachineOperand> Cond, in insertBranch() argument
232 assert((Cond.size() == 3 || Cond.size() == 0) && in insertBranch()
235 if (Cond.empty()) { in insertBranch()
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