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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c136 clks->num_levels = 6; in get_default_clock_levels()
141 clks->num_levels = 6; in get_default_clock_levels()
146 clks->num_levels = 2; in get_default_clock_levels()
151 clks->num_levels = 0; in get_default_clock_levels()
268 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels()
270 dc_clks->num_levels = pp_clks->count; in pp_to_dc_clock_levels()
275 for (i = 0; i < dc_clks->num_levels; i++) { in pp_to_dc_clock_levels()
288 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { in pp_to_dc_clock_levels_with_latency()
291 pp_clks->num_levels, in pp_to_dc_clock_levels_with_latency()
294 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels_with_latency()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
H A Damdgpu_dce112_resource.c1061 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1063 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1065 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1067 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1069 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1071 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1073 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1086 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, in bw_calcs_data_update_from_pplib()
1089 clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, in bw_calcs_data_update_from_pplib()
1097 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
H A Damdgpu_dce120_resource.c909 &eng_clks) || eng_clks.num_levels == 0) { in bw_calcs_data_update_from_pplib()
911 eng_clks.num_levels = 8; in bw_calcs_data_update_from_pplib()
914 for (i = 0; i < eng_clks.num_levels; i++) { in bw_calcs_data_update_from_pplib()
922 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
924 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
926 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
928 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
930 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
932 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
934 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_sumo_dpm.c352 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
359 for (i = 0; i < ps->num_levels - 1; i++) in sumo_program_bsp()
413 for (i = 0; i < ps->num_levels; i++) { in sumo_program_at()
414 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi; in sumo_program_at()
428 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) | in sumo_program_at()
429 CG_L(m_a * l[ps->num_levels - 1] / 100); in sumo_program_at()
675 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; in sumo_patch_boost_state()
748 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1)); in sumo_program_wl()
764 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in sumo_program_power_levels_0_to_n()
766 for (i = 0; i < new_ps->num_levels; i++) { in sumo_program_power_levels_0_to_n()
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H A Dradeon_trinity_dpm.c851 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in trinity_program_power_levels_0_to_n()
853 for (i = 0; i < new_ps->num_levels; i++) { in trinity_program_power_levels_0_to_n()
858 for (i = new_ps->num_levels; i < n_current_state_levels; i++) in trinity_program_power_levels_0_to_n()
974 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
975 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
988 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
989 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1214 if (ps->num_levels <= 1) in trinity_dpm_force_performance_level()
1221 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1); in trinity_dpm_force_performance_level()
1225 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_force_performance_level()
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H A Dr100_track.h46 unsigned num_levels; member
H A Dradeon_kv_dpm.c1732 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1739 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1758 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1767 new_ps->levels[new_ps->num_levels -1].sclk)) in kv_set_valid_clock_range()
2195 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2201 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2213 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2224 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2586 ps->num_levels = 1; in kv_patch_boot_state()
2631 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
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H A Dtrinity_dpm.h50 u32 num_levels; member
H A Dkv_dpm.h85 u32 num_levels; member
H A Dsumo_dpm.h49 u32 num_levels; member
H A Dradeon_r200.c424 track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK) in r200_packet0_check()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddm_services_types.h100 uint32_t num_levels; member
110 uint32_t num_levels; member
120 uint32_t num_levels; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
H A Damdgpu_dce110_resource.c1268 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1270 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1272 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1274 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1276 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1278 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1280 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1291 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1293 clks.clocks_in_khz[clks.num_levels>>1], 1000); in bw_calcs_data_update_from_pplib()
1306 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, in bw_calcs_data_update_from_pplib()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/
H A Ddm_pp_interface.h177 uint32_t num_levels; member
187 uint32_t num_levels; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
H A Damdgpu_dce110_clk_mgr.c81 if (dc->sclk_lvls.num_levels == 0) in determine_sclk_from_bounding_box()
84 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { in determine_sclk_from_bounding_box()
94 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; in determine_sclk_from_bounding_box()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_smu10_hwmgr.c1034 clocks->num_levels = 0; in smu10_get_clock_by_type_with_latency()
1037 clocks->data[clocks->num_levels].clocks_in_khz = in smu10_get_clock_by_type_with_latency()
1039 clocks->data[clocks->num_levels].latency_in_us = latency_required ? in smu10_get_clock_by_type_with_latency()
1043 clocks->num_levels++; in smu10_get_clock_by_type_with_latency()
1088 clocks->num_levels = 0; in smu10_get_clock_by_type_with_voltage()
1091 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10; in smu10_get_clock_by_type_with_voltage()
1092 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol; in smu10_get_clock_by_type_with_voltage()
1093 clocks->num_levels++; in smu10_get_clock_by_type_with_voltage()
H A Damdgpu_vega12_hwmgr.c1737 clocks->num_levels = ucount; in vega12_get_sclks()
1770 clocks->num_levels = data->mclk_latency_table.count = ucount; in vega12_get_memclocks()
1798 clocks->num_levels = ucount; in vega12_get_dcefclocks()
1826 clocks->num_levels = ucount; in vega12_get_socclocks()
1862 clocks->num_levels = 0; in vega12_get_clock_by_type_with_voltage()
2109 for (i = 0; i < clocks.num_levels; i++) in vega12_print_clock_levels()
2125 for (i = 0; i < clocks.num_levels; i++) in vega12_print_clock_levels()
2143 for (i = 0; i < clocks.num_levels; i++) in vega12_print_clock_levels()
2161 for (i = 0; i < clocks.num_levels; i++) in vega12_print_clock_levels()
H A Damdgpu_vega20_hwmgr.c2775 clocks->num_levels = count; in vega20_get_sclks()
2803 clocks->num_levels = data->mclk_latency_table.count = count; in vega20_get_memclocks()
2828 clocks->num_levels = count; in vega20_get_dcefclocks()
2850 clocks->num_levels = count; in vega20_get_socclocks()
2892 clocks->num_levels = 0; in vega20_get_clock_by_type_with_voltage()
3292 for (i = 0; i < clocks.num_levels; i++) in vega20_print_clock_levels()
3310 for (i = 0; i < clocks.num_levels; i++) in vega20_print_clock_levels()
3328 for (i = 0; i < clocks.num_levels; i++) in vega20_print_clock_levels()
3358 for (i = 0; i < clocks.num_levels; i++) in vega20_print_clock_levels()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
H A Damdgpu_dcn_calcs.c1427 if (clks->num_levels == 0) in verify_clock_values()
1430 for (i = 0; i < clks->num_levels; i++) in verify_clock_values()
1455 ASSERT(fclks.num_levels); in dcn_bw_update_from_pplib()
1458 vmid0p72_idx = fclks.num_levels - in dcn_bw_update_from_pplib()
1459 (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1)); in dcn_bw_update_from_pplib()
1460 vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1); in dcn_bw_update_from_pplib()
1461 vmax0p9_idx = fclks.num_levels - 1; in dcn_bw_update_from_pplib()
1490 if (res && dcfclks.num_levels >= 3) { in dcn_bw_update_from_pplib()
1492 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0; in dcn_bw_update_from_pplib()
1493 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0; in dcn_bw_update_from_pplib()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_kv_dpm.c1796 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1803 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1822 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1831 new_ps->levels[new_ps->num_levels -1].sclk)) in kv_set_valid_clock_range()
2260 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2266 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2278 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2289 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2654 ps->num_levels = 1; in kv_patch_boot_state()
2699 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
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H A Dkv_dpm.h111 u32 num_levels; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_arcturus_ppt.c603 clocks->num_levels = count; in arcturus_get_clk_table()
655 for (i = 0; i < clocks.num_levels; i++) in arcturus_print_clk_levels()
658 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
678 for (i = 0; i < clocks.num_levels; i++) in arcturus_print_clk_levels()
681 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
701 for (i = 0; i < clocks.num_levels; i++) in arcturus_print_clk_levels()
704 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
727 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c583 if (dc->sclk_lvls.num_levels == 0) in determine_sclk_from_bounding_box()
586 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { in determine_sclk_from_bounding_box()
596 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; in determine_sclk_from_bounding_box()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_debugfs.c3230 int num_levels; in wm_latency_show() local
3233 num_levels = 3; in wm_latency_show()
3235 num_levels = 1; in wm_latency_show()
3237 num_levels = 3; in wm_latency_show()
3239 num_levels = ilk_wm_max_level(dev_priv) + 1; in wm_latency_show()
3243 for (level = 0; level < num_levels; level++) { in wm_latency_show()
3347 int num_levels; in wm_latency_write() local
3353 num_levels = 3; in wm_latency_write()
3355 num_levels = 1; in wm_latency_write()
3357 num_levels = 3; in wm_latency_write()
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H A Dintel_pm.c1226 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); in g4x_raw_plane_wm_compute() local
1238 for (level = 0; level < num_levels; level++) { in g4x_raw_plane_wm_compute()
1790 int num_levels = intel_wm_num_levels(dev_priv); in vlv_raw_plane_wm_set() local
1793 for (; level < num_levels; level++) { in vlv_raw_plane_wm_set()
1809 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); in vlv_raw_plane_wm_compute() local
1818 for (level = 0; level < num_levels; level++) { in vlv_raw_plane_wm_compute()
1924 wm_state->num_levels = intel_wm_num_levels(dev_priv); in vlv_compute_pipe_wm()
1932 for (level = 0; level < wm_state->num_levels; level++) { in vlv_compute_pipe_wm()
1960 wm_state->num_levels = level; in vlv_compute_pipe_wm()
2088 intermediate->num_levels = min(optimal->num_levels, active->num_levels); in vlv_compute_intermediate_wm()
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