| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUArgumentUsageInfo.cpp | 152 = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3); in fixedABILayout()
153 AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5); in fixedABILayout()
154 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7); in fixedABILayout()
158 AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9); in fixedABILayout()
159 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11); in fixedABILayout()
162 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12); in fixedABILayout()
163 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13); in fixedABILayout()
164 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14); in fixedABILayout()
167 AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask); in fixedABILayout()
168 AI.WorkItemIDY = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 10); in fixedABILayout()
[all …]
|
| H A D | SIMachineFunctionInfo.cpp | 79 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
134 ArgDescriptor::createRegister(AMDGPU::SGPR5); in SIMachineFunctionInfo()
201 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
208 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
215 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
223 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
230 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
237 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
244 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addImplicitBufferPtr()
|
| H A D | SIMachineFunctionInfo.h | 580 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
586 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
592 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
598 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
618 = ArgDescriptor::createRegister(getNextSystemSGPR());
624 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
|
| H A D | AMDGPUArgumentUsageInfo.h | 44 static constexpr ArgDescriptor createRegister(Register Reg,
|
| H A D | AMDGPUTargetMachine.cpp | 1322 Arg = ArgDescriptor::createRegister(Reg); in parseMachineFunctionInfo()
|
| H A D | SIISelLowering.cpp | 1837 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask)); in allocateSpecialEntryInputVGPRs()
1843 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
1850 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
1857 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
1864 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
1895 return ArgDescriptor::createRegister(Reg, Mask); in allocateVGPR32Input()
1912 return ArgDescriptor::createRegister(Reg); in allocateSGPR32InputImpl()
1974 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask)); in allocateSpecialInputVGPRsFixed()
1975 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg, Mask << 10)); in allocateSpecialInputVGPRsFixed()
1976 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg, Mask << 20)); in allocateSpecialInputVGPRsFixed()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfExpression.cpp | 104 DwarfRegs.push_back(Register::createRegister(-1, nullptr)); in addMachineReg()
114 DwarfRegs.push_back(Register::createRegister(Reg, nullptr)); in addMachineReg()
126 DwarfRegs.push_back(Register::createRegister(Reg, "super-register")); in addMachineReg()
166 DwarfRegs.push_back(Register::createRegister(Reg, "sub-register")); in addMachineReg()
|
| H A D | DwarfExpression.h | 115 static Register createRegister(int RegNo, const char *Comment) { in createRegister() function
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcFrameLowering.cpp | 168 MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA)); in emitPrologue()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | CFIInstrInserter.cpp | 371 MCCFIInstruction::createRegister(nullptr, Reg, *RO.Reg)); in insertCFIInstrs()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCDwarf.h | 530 static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, in createRegister() function
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/ |
| H A D | MCStreamer.cpp | 635 MCCFIInstruction::createRegister(Label, Register1, Register2); in emitCFIRegister()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 1209 unsigned CFIRegister = MF.addFrameInst(MCCFIInstruction::createRegister( in emitPrologue()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 2299 MF.addFrameInst(MCCFIInstruction::createRegister(nullptr, Reg, Reg2)); in parseCFIOperand()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 6312 MCCFIInstruction::createRegister(nullptr, DwarfLR, DwarfReg)); in emitCFIForLRSaveToReg()
|