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Searched refs:addDef (Results 1 – 25 of 45) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp276 .addDef(Dest) in buildUnalignedLoad()
326 .addDef(PseudoMULTuReg) in select()
333 .addDef(I.getOperand(0).getReg()) in select()
375 .addDef(JTIndex) in select()
383 .addDef(DestAddress) in select()
392 .addDef(Dest) in select()
404 .addDef(Dest) in select()
482 .addDef(ImplDef); in select()
519 .addDef(HILOReg) in select()
527 .addDef(I.getOperand(0).getReg()) in select()
[all …]
H A DMipsISelLowering.cpp4751 .addDef(Temp) in emitLDR_W()
4754 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); in emitLDR_W()
4761 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef); in emitLDR_W()
4763 .addDef(LoadHalf) in emitLDR_W()
4768 .addDef(LoadFull) in emitLDR_W()
4772 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); in emitLDR_W()
4798 .addDef(Temp) in emitLDR_D()
4801 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); in emitLDR_D()
4807 .addDef(Lo) in emitLDR_D()
4811 .addDef(Hi) in emitLDR_D()
[all …]
H A DMipsCallLowering.cpp129 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
535 MIB.addDef(Mips::SP, RegState::Implicit); in lowerCall()
600 MIB.addDef(Mips::GP, RegState::Implicit); in lowerCall()
H A DMipsSEISelDAGToDAG.cpp134 .addDef(Mips::AT_64) in emitMCountABI()
142 .addDef(Mips::AT) in emitMCountABI()
147 .addDef(Mips::SP) in emitMCountABI()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp232 .addDef(MisspeculatingTaintReg) in insertTrackingCode()
370 .addDef(AArch64::XZR) in insertSPToRegTaintPropagation()
376 .addDef(MisspeculatingTaintReg) in insertSPToRegTaintPropagation()
393 .addDef(TmpReg) in insertRegToSPTaintPropagation()
399 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation()
405 .addDef(AArch64::SP) in insertRegToSPTaintPropagation()
453 .addDef(Reg) in makeGPRSpeculationSafe()
577 .addDef(DstReg) in expandSpeculationSafeValue()
H A DAArch64LowerHomogeneousPrologEpilog.cpp210 MIB.addDef(AArch64::SP); in emitStore()
233 MIB.addDef(AArch64::SP); in emitLoad()
312 .addDef(AArch64::FP) in getOrCreateFrameHelper()
327 .addDef(AArch64::X16) in getOrCreateFrameHelper()
556 .addDef(AArch64::FP) in lowerProlog()
H A DAArch64ExpandPseudoInsts.cpp600 .addDef(AddressReg) in expandSetTagLoop()
607 .addDef(SizeReg) in expandSetTagLoop()
932 .addDef(Reg32) in expandMI()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp763 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); in expandPseudoLogM()
764 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); in expandPseudoLogM()
768 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); in expandPseudoLogM()
769 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); in expandPseudoLogM()
897 .addDef(VMX) in expandPostRAPseudo()
903 .addDef(VMX) in expandPostRAPseudo()
911 .addDef(VMX) in expandPostRAPseudo()
920 .addDef(VMX) in expandPostRAPseudo()
1070 .addDef(MI.getOperand(0).getReg()) in expandGetStackTopPseudo()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp495 .addDef(DestReg) in putConstant()
599 .addDef(ResReg) in insertComparison()
696 .addDef(ResultReg) in selectGlobal()
793 .addDef(ResReg) in selectSelect()
887 .addDef(SExtResult) in select()
936 .addDef(DstReg) in select()
937 .addDef(IgnoredBits) in select()
1108 .addDef(ValueToStore) in select()
H A DARMLowOverheadLoops.cpp1343 MIB.addDef(ARM::LR); in RevertLoopEndDec()
1428 MIB.addDef(ARM::LR); in ExpandLoopStart()
1588 MIB.addDef(ARM::LR); in Expand()
H A DThumb1FrameLowering.cpp419 .addDef(ARM::CPSR) in emitPrologue()
425 .addDef(ARM::CPSR) in emitPrologue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp264 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildConstant()
297 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildFConstant()
720 MIB.addDef(ResultReg); in buildIntrinsic()
804 .addDef(OldValRes) in buildAtomicCmpXchgWithSuccess()
805 .addDef(SuccessRes) in buildAtomicCmpXchgWithSuccess()
830 .addDef(OldValRes) in buildAtomicCmpXchg()
957 return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA); in buildBlockAddress()
H A DRegBankSelect.cpp165 .addDef(Dst) in repairReg()
195 .addDef(MO.getReg()); in repairReg()
205 UnMergeBuilder.addDef(DefReg); in repairReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRRelaxMemOperations.cpp116 .addDef(Ptr.getReg(), getKillRegState(Ptr.isKill())); in relax()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp662 .addDef(LoLHS) in split64BitValueForMapping()
663 .addDef(HiLHS) in split64BitValueForMapping()
758 .addDef(InitSaveExecReg); in executeInWaterfallLoop()
787 .addDef(PhiExec) in executeInWaterfallLoop()
795 .addDef(std::get<2>(Result)) in executeInWaterfallLoop()
872 .addDef(NewCondReg) in executeInWaterfallLoop()
882 .addDef(AndReg) in executeInWaterfallLoop()
966 .addDef(NewCondReg) in executeInWaterfallLoop()
975 .addDef(AndReg) in executeInWaterfallLoop()
1004 .addDef(NewExec) in executeInWaterfallLoop()
[all …]
H A DAMDGPUInstructionSelector.cpp338 .addDef(UnusedCarry, RegState::Dead) in selectG_ADD_SUB()
372 .addDef(CarryReg) in selectG_ADD_SUB()
377 .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead) in selectG_ADD_SUB()
887 .addDef(Dst1) in selectDivScale()
1650 MIB.addDef(TmpReg); in selectImageIntrinsic()
1657 MIB.addDef(VDataOut); // vdata output in selectImageIntrinsic()
3968 .addDef(RSrc2) in buildRSRC()
3971 .addDef(RSrc3) in buildRSRC()
3978 .addDef(RSrcHi) in buildRSRC()
3988 .addDef(RSrcLo) in buildRSRC()
[all …]
H A DSIShrinkInstructions.cpp562 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
563 .addDef(Y1.Reg, 0, Y1.SubReg) in matchSwap()
H A DAMDGPULegalizerInfo.cpp1758 .addDef(GetReg) in getSegmentAperture()
2262 .addDef(PCReg); in buildPCRelGlobalAddress()
2509 .addDef(DstReg) in legalizeAtomicCmpXChg()
3833 .addDef(LoadDstReg) // vdata in legalizeBufferLoad()
3874 .addDef(MI.getOperand(0).getReg()) in legalizeAtomicIncDec()
3992 MIB.addDef(Dst); in legalizeBufferAtomic()
4665 .addDef(DstReg) in legalizeBVHIntrinsic()
4709 .addDef(Def) in legalizeIntrinsic()
4714 .addDef(Def) in legalizeIntrinsic()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86CallLowering.cpp229 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
346 .addDef(X86::AL) in lowerCall()
H A DX86InstructionSelector.cpp257 .addDef(ExtSrc) in selectCopy()
883 .addDef(DstReg) in selectAnyext()
1660 .addDef(DstReg) in selectDivRem()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h76 MIB.addDef(Reg); in addDefToMIB()
79 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy)); in addDefToMIB()
82 MIB.addDef(MRI.createVirtualRegister(RC)); in addDefToMIB()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp796 .addDef(Hexagon::D15) in insertEpilogueInBlock()
846 .addDef(Hexagon::D15) in insertEpilogueInBlock()
852 .addDef(Hexagon::D15) in insertEpilogueInBlock()
873 .addDef(Hexagon::D15) in insertEpilogueInBlock()
904 .addDef(SP) in insertAllocframe()
916 .addDef(SP) in insertAllocframe()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DLiveDebugVariables.cpp414 void addDef(SlotIndex Idx, ArrayRef<MachineOperand> LocMOs, bool IsIndirect, in addDef() function in __anonfbf3834f0411::UserValue
830 UV->addDef(Idx, in handleDebugValue()
841 UV->addDef(Idx, UndefMOs, false, IsList, *Expr); in handleDebugValue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp211 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
1146 MIB.addDef(AArch64::X21, RegState::Implicit); in lowerCall()
H A DAArch64InstructionSelector.cpp1781 .addDef(ArgsAddrReg) in selectVaStartDarwin()
1817 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
2544 .addDef(SrcReg) in select()
2653 IsStore ? NewInst.addUse(ValReg) : NewInst.addDef(ValReg); in select()
2924 .addDef(ExtSrc) in select()
3338 .addDef(AArch64::X0, RegState::Implicit) in selectTLSGlobalValue()
3699 .addDef(SubToRegDef) in selectMergeValues()
3707 .addDef(SubToRegDef2) in selectMergeValues()
3713 .addDef(I.getOperand(0).getReg()) in selectMergeValues()

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