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Searched refs:ValReg (Results 1 – 15 of 15) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp111 unsigned ValReg; in EmitTargetCodeForMemset() local
118 ValReg = X86::EAX; in EmitTargetCodeForMemset()
123 ValReg = X86::RAX; in EmitTargetCodeForMemset()
129 ValReg = X86::AX; in EmitTargetCodeForMemset()
134 ValReg = X86::AL; in EmitTargetCodeForMemset()
144 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
H A DX86FastISel.cpp92 bool X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM,
487 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM, in X86FastEmitStore() argument
507 .addReg(ValReg).addImm(1); in X86FastEmitStore()
508 ValReg = AndResult; in X86FastEmitStore()
650 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
653 addFullAddress(MIB, AM).addReg(ValReg); in X86FastEmitStore()
697 Register ValReg = getRegForValue(Val); in X86FastEmitStore() local
698 if (ValReg == 0) in X86FastEmitStore()
701 return X86FastEmitStore(VT, ValReg, AM, MMO, Aligned); in X86FastEmitStore()
/netbsd-src/external/gpl3/gdb/dist/sim/arm/
H A Darmcopro.c1118 static ARMword ValReg[16]; variable
1132 ValReg[BITS (12, 15)] = data; in ValLDC()
1155 * data = ValReg[BITS (12, 15)]; in ValSTC()
1172 *value = ValReg[BITS (16, 19)]; in ValMRC()
1183 ValReg[BITS (16, 19)] = value; in ValMCR()
1200 howlong = ValReg[BITS (0, 3)]; in ValCDP()
1240 howlong = ValReg[BITS (0, 3)]; in IntCDP()
1286 ValReg[BITS (0, 3)] = ARMul_Time (state); in IntCDP()
/netbsd-src/external/gpl3/gcc/dist/libphobos/libdruntime/core/internal/
H A Datomic.d246 enum ValReg = SizedReg!(AX, T); in version() local
255 }, [DestReg, ValReg])); in version()
262 enum ValReg = SizedReg!(CX, T); in version() local
267 enum ValReg = SizedReg!(DI, T); in version() local
279 }, [DestReg, ValReg, ResReg])); in version()
299 enum ValReg = SizedReg!(AX, T); in version() local
308 }, [DestReg, ValReg])); in version()
315 enum ValReg = SizedReg!(CX, T); in version() local
320 enum ValReg = SizedReg!(DI, T); in version() local
332 }, [DestReg, ValReg, ResReg])); in version()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp380 MachineBasicBlock *MBB, Register ValReg, in insertSext() argument
382 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
383 .addReg(ValReg) in insertSext()
385 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
386 .addReg(ValReg) in insertSext()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp233 Register extendRegister(Register ValReg, const CCValAssign &VA);
291 Register MipsOutgoingValueHandler::extendRegister(Register ValReg, in extendRegister() argument
296 return MIRBuilder.buildSExt(LocTy, ValReg).getReg(0); in extendRegister()
299 return MIRBuilder.buildZExt(LocTy, ValReg).getReg(0); in extendRegister()
302 return MIRBuilder.buildAnyExt(LocTy, ValReg).getReg(0); in extendRegister()
306 return ValReg; in extendRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp1052 Register CallLowering::ValueHandler::extendRegister(Register ValReg, in extendRegister() argument
1059 return ValReg; in extendRegister()
1063 return ValReg; in extendRegister()
1073 return ValReg; in extendRegister()
1075 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
1080 MIRBuilder.buildSExt(NewReg, ValReg); in extendRegister()
1085 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
H A DLegalizerHelper.cpp3867 Register ValReg = MI.getOperand(0).getReg(); in reduceLoadStoreWidth() local
3869 LLT ValTy = MRI.getType(ValReg); in reduceLoadStoreWidth()
3884 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, in reduceLoadStoreWidth()
3937 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, in reduceLoadStoreWidth()
6763 Register ValReg = MI.getOperand(ValRegIndex).getReg(); in lowerReadWriteRegister() local
6764 const LLT Ty = MRI.getType(ValReg); in lowerReadWriteRegister()
6773 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
6775 MIRBuilder.buildCopy(PhysReg, ValReg); in lowerReadWriteRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp426 Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register(); in canSinkLoadStoreTo() local
435 if (ValReg && MI->readsVirtualRegister(ValReg)) in canSinkLoadStoreTo()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp1899 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
1903 .addReg(ValReg) in emitInstruction()
1910 .addReg(ValReg) in emitInstruction()
1913 .addReg(ValReg) in emitInstruction()
1920 .addReg(ValReg) in emitInstruction()
1965 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
1969 .addReg(ValReg) in emitInstruction()
1979 .addReg(ValReg) in emitInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp946 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoadStore() local
947 const LLT ValTy = MRI.getType(ValReg); in legalizeLoadStore()
959 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore()
963 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore()
H A DAArch64InstructionSelector.cpp2630 const Register ValReg = I.getOperand(0).getReg(); in select() local
2631 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
2653 IsStore ? NewInst.addUse(ValReg) : NewInst.addDef(ValReg); in select()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h295 Register extendRegister(Register ValReg, CCValAssign &VA,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp1282 Register ValReg = MI.getOperand(3).getReg(); in selectDSOrderedIntrinsic() local
1285 .addReg(ValReg) in selectDSOrderedIntrinsic()
2692 Register ValReg = MI.getOperand(2).getReg(); in selectG_INSERT_VECTOR_ELT() local
2696 LLT ValTy = MRI->getType(ValReg); in selectG_INSERT_VECTOR_ELT()
2701 const RegisterBank *ValRB = RBI.getRegBank(ValReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
2718 !RBI.constrainGenericRegister(ValReg, *ValRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2743 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
2753 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
H A DAMDGPULegalizerInfo.cpp2410 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoad() local
2411 LLT ValTy = MRI.getType(ValReg); in legalizeLoad()
2445 B.buildTrunc(ValReg, WideLoad).getReg(0); in legalizeLoad()
2453 B.buildExtract(ValReg, WideLoad, 0); in legalizeLoad()
2458 WideLoad = Helper.widenWithUnmerge(WideTy, ValReg); in legalizeLoad()