Searched refs:SRsrc (Results 1 – 3 of 3) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 189 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr, 192 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr, 198 SDValue Addr, SDValue &SRsrc, SDValue &Soffset, 201 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset, 1473 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, in SelectMUBUFAddr64() argument 1493 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64() 1592 SDValue &SRsrc, in SelectMUBUFScratchOffset() argument 1603 SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); in SelectMUBUFScratchOffset() 1617 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, in SelectMUBUFOffset() argument 1637 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset() [all …]
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| H A D | SILoadStoreOptimizer.cpp | 87 bool SRsrc = false; member 433 Result.SRsrc = true; in getRegs() 448 Result.SRsrc = true; in getRegs() 459 Result.SRsrc = true; in getRegs() 548 if (Regs.SRsrc) in setMI()
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| H A D | SIInstrInfo.cpp | 5202 Register SRsrc = MRI.createVirtualRegister(SRsrcRC); in emitLoadSRsrcFromVGPRLoop() local 5205 auto Merge = BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc); in emitLoadSRsrcFromVGPRLoop() 5213 Rsrc.setReg(SRsrc); in emitLoadSRsrcFromVGPRLoop() 5505 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc); in legalizeOperands() local 5506 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) in legalizeOperands() 5507 CreatedBB = loadSRsrcFromVGPR(*this, MI, *SRsrc, MDT); in legalizeOperands()
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