| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 43 MVT RegisterVT = TLI.getRegisterType(F.getContext(), VT); in computeLegalValueVTs() local
45 ValueVTs.push_back(RegisterVT); in computeLegalValueVTs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 73 MVT RegisterVT = TLI.getRegisterTypeForCallingConv( in handle() local
76 VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT})); in handle()
347 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT, in determineLocInfo() argument
351 if (VT.getFixedSizeInBits() >= RegisterVT.getFixedSizeInBits()) in determineLocInfo()
648 MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(), in subTargetRegTypeForCallingConv() local
661 ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo], in subTargetRegTypeForCallingConv()
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| H A D | MipsISelLowering.h | 302 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | MipsISelLowering.cpp | 131 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
133 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); in getVectorTypeBreakdownForCallingConv()
134 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
136 VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits() in getVectorTypeBreakdownForCallingConv()
138 : divideCeil(VT.getSizeInBits(), RegisterVT.getSizeInBits()); in getVectorTypeBreakdownForCallingConv()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1071 MVT &RegisterVT, in getVectorTypeBreakdownMVT() argument
1116 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1437 MVT RegisterVT; in computeRegisterProperties() local
1440 NumIntermediates, RegisterVT, this); in computeRegisterProperties()
1444 RegisterTypeForVT[i] = RegisterVT; in computeRegisterProperties()
1506 MVT &RegisterVT) const { in getVectorTypeBreakdown()
1520 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1553 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1580 RegisterVT = DestVT; in getVectorTypeBreakdown()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 340 MVT RegisterVT; in getCopyFromPartsVector() local
347 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
351 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
356 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyFromPartsVector()
357 assert(RegisterVT.getSizeInBits() == in getCopyFromPartsVector()
694 MVT RegisterVT; in getCopyToPartsVector() local
700 NumIntermediates, RegisterVT); in getCopyToPartsVector()
704 NumIntermediates, RegisterVT); in getCopyToPartsVector()
709 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyToPartsVector()
794 MVT RegisterVT = in RegsForValue() local
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| H A D | FunctionLoweringInfo.cpp | 395 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
399 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
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| H A D | FastISel.cpp | 1014 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
1018 MyFlags.VT = RegisterVT; in lowerCallTo()
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| H A D | SelectionDAG.cpp | 2161 MVT RegisterVT; in getReducedAlign() local
2164 NumIntermediates, RegisterVT); in getReducedAlign()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 970 MVT &RegisterVT) const;
977 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
979 RegisterVT); in getVectorTypeBreakdownForCallingConv()
1455 MVT RegisterVT; in getRegisterType() local
1458 NumIntermediates, RegisterVT); in getRegisterType()
1459 return RegisterVT; in getRegisterType()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1054 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); in analyzeFormalArgumentsCompute() local
1062 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1066 } else if (ArgVT.isVector() && RegisterVT.isVector() && in analyzeFormalArgumentsCompute()
1067 ArgVT.getScalarType() == RegisterVT.getScalarType()) { in analyzeFormalArgumentsCompute()
1068 assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements()); in analyzeFormalArgumentsCompute()
1072 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1080 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1084 if (RegisterVT.isInteger()) { in analyzeFormalArgumentsCompute()
1086 } else if (RegisterVT.isVector()) { in analyzeFormalArgumentsCompute()
1087 assert(!RegisterVT.getScalarType().isFloatingPoint()); in analyzeFormalArgumentsCompute()
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| H A D | SIISelLowering.h | 44 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | SIISelLowering.cpp | 937 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
946 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16; in getVectorTypeBreakdownForCallingConv()
947 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
953 RegisterVT = ScalarVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
954 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
961 RegisterVT = MVT::i16; in getVectorTypeBreakdownForCallingConv()
969 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
976 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
977 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
984 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1396 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | X86ISelLowering.cpp | 2157 MVT RegisterVT; in getRegisterTypeForCallingConv() local
2159 std::tie(RegisterVT, NumRegisters) = in getRegisterTypeForCallingConv()
2161 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getRegisterTypeForCallingConv()
2162 return RegisterVT; in getRegisterTypeForCallingConv()
2175 MVT RegisterVT; in getNumRegistersForCallingConv() local
2177 std::tie(RegisterVT, NumRegisters) = in getNumRegistersForCallingConv()
2179 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getNumRegistersForCallingConv()
2188 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
2195 RegisterVT = MVT::i8; in getVectorTypeBreakdownForCallingConv()
2204 RegisterVT = MVT::v32i8; in getVectorTypeBreakdownForCallingConv()
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