Searched refs:ConvInput (Results 1 – 3 of 3) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12524 SDValue ConvInput = Op.getOperand(0); in performFDivCombine() local
12527 ConvInput = DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, in performFDivCombine()
12528 ResTy, ConvInput); in performFDivCombine()
12533 DAG.getConstant(IntrinsicOpcode, DL, MVT::i32), ConvInput, in performFDivCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 20968 SDValue ConvInput = V->getOperand(0); in visitVECTOR_SHUFFLE() local
20969 if (ConvInput.getValueType().isVector() && in visitVECTOR_SHUFFLE()
20970 ConvInput.getValueType().getVectorNumElements() == NumElts) in visitVECTOR_SHUFFLE()
20971 V = ConvInput.getNode(); in visitVECTOR_SHUFFLE()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 15544 SDValue ConvInput = Op.getOperand(0); in PerformVDIVCombine() local
15546 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PerformVDIVCombine()
15548 ConvInput); in PerformVDIVCombine()
15555 ConvInput, DAG.getConstant(C, dl, MVT::i32)); in PerformVDIVCombine()
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