| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 559 const SrcOp &CarryIn) { in buildUAdde() argument
561 {Op0, Op1, CarryIn}); in buildUAdde()
567 const SrcOp &CarryIn) { in buildUSube() argument
569 {Op0, Op1, CarryIn}); in buildUSube()
575 const SrcOp &CarryIn) { in buildSAdde() argument
577 {Op0, Op1, CarryIn}); in buildSAdde()
583 const SrcOp &CarryIn) { in buildSSube() argument
585 {Op0, Op1, CarryIn}); in buildSSube()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoVPseudos.td | 1017 bit CarryIn,
1020 !if(CarryIn,
1661 // For vadc and vsbc, CarryIn == 1 and CarryOut == 0
1662 multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1,
1665 def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
1667 !if(!and(CarryIn, !not(CarryOut)),
1669 m.vrclass, m.vrclass, m, CarryIn, Constraint>;
1672 multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
1675 def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
1677 !if(!and(CarryIn, !not(CarryOut)),
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIPeepholeSDWA.cpp | 876 MachineOperand *CarryIn = TII->getNamedOperand(MISucc, AMDGPU::OpName::src2); in pseudoOpConvertToVOP2() local
877 if (!CarryIn) in pseudoOpConvertToVOP2()
882 if (!MRI->hasOneUse(CarryIn->getReg()) || !MRI->use_empty(CarryOut->getReg())) in pseudoOpConvertToVOP2()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1719 Optional<Register> CarryIn = None; in widenScalarAddSubOverflow() local
1742 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
1747 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
1752 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
1757 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
1765 if (CarryIn) { in widenScalarAddSubOverflow()
1769 {LHSExt, RHSExt, *CarryIn}) in widenScalarAddSubOverflow()
3069 Register CarryIn = MI.getOperand(4).getReg(); in lower() local
3073 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); in lower()
4784 Register CarryIn; in narrowScalarAddSub() local
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 416 SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
2860 SDValue CarryIn = N->getOperand(2); in visitADDE() local
2867 N1, N0, CarryIn); in visitADDE()
2870 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitADDE()
2879 SDValue CarryIn = N->getOperand(2); in visitADDCARRY() local
2886 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn); in visitADDCARRY()
2889 if (isNullConstant(CarryIn)) { in visitADDCARRY()
2898 EVT CarryVT = CarryIn.getValueType(); in visitADDCARRY()
2899 SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT); in visitADDCARRY()
2906 if (SDValue Combined = visitADDCARRYLike(N0, N1, CarryIn, N)) in visitADDCARRY()
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| H A D | TargetLowering.cpp | 8312 SDValue CarryIn = DAG.getConstant(0, dl, Node->getValueType(1)); in expandUADDSUBO() local
8314 { LHS, RHS, CarryIn }); in expandUADDSUBO()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 536 Value *CarryIn = II.getArgOperand(0); in simplifyX86addcarry() local
546 if (match(CarryIn, PatternMatch::m_ZeroInt())) { in simplifyX86addcarry()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2617 SDValue CarryIn = N->getOperand(FirstInputOp + 2); in SelectMVE_VADCSBC() local
2618 ConstantSDNode *CarryInConstant = dyn_cast<ConstantSDNode>(CarryIn); in SelectMVE_VADCSBC()
2625 Ops.push_back(CarryIn); in SelectMVE_VADCSBC()
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