Searched refs:control (Results 1 – 25 of 85) sorted by relevance
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| /dpdk/drivers/raw/ifpga/base/ |
| H A D | ifpga_feature_dev.c | 19 struct feature_port_control control; in __fpga_port_enable() local
30 control.csr = readq(&port_hdr->control); in __fpga_port_enable()
31 control.port_sftrst = 0x0; in __fpga_port_enable()
32 writeq(control.csr, &port_hdr->control); in __fpga_port_enable()
38 struct feature_port_control control; in __fpga_port_disable() local
48 control.csr = readq(&port_hdr->control); in __fpga_port_disable()
49 control.port_sftrst = 0x1; in __fpga_port_disable()
50 writeq(control.csr, &port_hdr->control); in __fpga_port_disable()
57 control.port_sftrst_ack = 1; in __fpga_port_disable()
59 if (fpga_wait_register_field(port_sftrst_ack, control, in __fpga_port_disable()
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| H A D | ifpga_port.c | 83 struct feature_port_control control; in port_get_latency_tolerance() local
88 control.csr = readq(&port_hdr->control); in port_get_latency_tolerance()
89 *val = control.latency_tolerance; in port_get_latency_tolerance()
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| /dpdk/drivers/net/qede/base/ |
| H A D | ecore_hw.c | 61 p_pool->ptts[i].pxp.pretend.control = 0; in ecore_ptt_pool_alloc()
371 u16 control = 0; in ecore_fid_pretend() local
373 SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); in ecore_fid_pretend()
374 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); in ecore_fid_pretend()
378 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); in ecore_fid_pretend()
379 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); in ecore_fid_pretend()
380 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); in ecore_fid_pretend()
385 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control); in ecore_fid_pretend()
397 u16 control = 0; in ecore_port_pretend() local
399 SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id); in ecore_port_pretend()
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| /dpdk/lib/eal/common/ |
| H A D | eal_common_proc.c | 268 char control[CMSG_SPACE(sizeof(m->msg.fds))]; in read_msg() local
280 msgh.msg_control = control; in read_msg()
281 msgh.msg_controllen = sizeof(control); in read_msg()
695 char control[CMSG_SPACE(fd_size)]; in send_msg() local
705 memset(control, 0, sizeof(control)); in send_msg()
714 msgh.msg_control = control; in send_msg()
715 msgh.msg_controllen = sizeof(control); in send_msg()
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| /dpdk/doc/guides/nics/features/ |
| H A D | failsafe.ini | 20 Flow control = Y
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| H A D | tap.ini | 20 Flow control = Y
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| H A D | mvpp2.ini | 16 Flow control = Y
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| H A D | octeontx.ini | 26 Flow control = Y
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| H A D | qede_vf.ini | 20 Flow control = Y
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| H A D | atlantic.ini | 20 Flow control = Y
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| H A D | e1000.ini | 18 Flow control = Y
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| H A D | ionic.ini | 26 Flow control = Y
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| H A D | igb.ini | 26 Flow control = Y
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| H A D | qede.ini | 21 Flow control = Y
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| H A D | mlx4.ini | 23 Flow control = Y
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| H A D | igc.ini | 31 Flow control = Y
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| H A D | hinic.ini | 34 Flow control = Y
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| H A D | ngbe.ini | 27 Flow control = Y
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| H A D | cxgbe.ini | 18 Flow control = Y
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| H A D | ipn3ke.ini | 27 Flow control = Y
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| /dpdk/doc/guides/prog_guide/ |
| H A D | pdcp_lib.rst | 19 #. Transfer of control plane data
37 PDCP library provides following control path API that is used to
82 PDCP packet processing API for control PDU
112 For example, when control PDUs are received, no cryptodev enqueue-dequeue is expected
222 * - Any control PDUs received would be processed and
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| H A D | glossary.rst | 27 The control plane is concerned with the routing of packets and with
45 In contrast to the control plane, the data plane in a network architecture
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| /dpdk/lib/vhost/ |
| H A D | socket.c | 107 char control[CMSG_SPACE(max_fds * sizeof(int))]; in read_fd_message() local
120 msgh.msg_control = control; in read_fd_message()
121 msgh.msg_controllen = sizeof(control); in read_fd_message()
136 VHOST_CONFIG_LOG(ifname, ERR, "truncated control data (fd %d)", sockfd); in read_fd_message()
163 char control[CMSG_SPACE(fdsize)]; in send_fd_message() local
175 msgh.msg_control = control; in send_fd_message()
176 msgh.msg_controllen = sizeof(control); in send_fd_message()
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| /dpdk/doc/guides/nics/ |
| H A D | memif.rst | 30 net_memif1, and so on. Memif uses unix domain socket to transmit control
69 For detailed information on memif control messages, see: net/memif/memif.h.
73 connected socket (control channel). Then it sends the 'hello' message
77 uses this id to find server interface, and assigns the control channel to this
92 - net/memif/memif.h *- control messages definitions*
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| H A D | netvsc.rst | 67 is to use the `driverctl Device Driver control utility`_ to override
74 .. _`driverctl Device Driver control utility`: https://gitlab.com/driverctl/driverctl
138 The rx_extmbuf_enable is used to control if netvsc should use external
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