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Searched refs:FWDSTEP (Results 1 – 16 of 16) sorted by relevance

/dpdk/examples/l3fwd/
H A Dl3fwd_lpm_sse.h14 processx4_step1(struct rte_mbuf *pkt[FWDSTEP], in processx4_step1() argument
54 struct rte_mbuf *pkt[FWDSTEP], in processx4_step2() argument
55 uint16_t dprt[FWDSTEP]) in processx4_step2() argument
90 __m128i dip[MAX_PKT_BURST / FWDSTEP]; in l3fwd_lpm_process_packets()
91 uint32_t ipv4_flag[MAX_PKT_BURST / FWDSTEP]; in l3fwd_lpm_process_packets()
92 const int32_t k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP); in l3fwd_lpm_process_packets()
94 for (j = 0; j != k; j += FWDSTEP) in l3fwd_lpm_process_packets()
95 processx4_step1(&pkts_burst[j], &dip[j / FWDSTEP], in l3fwd_lpm_process_packets()
96 &ipv4_flag[j / FWDSTEP]); in l3fwd_lpm_process_packets()
98 for (j = 0; j != k; j += FWDSTEP) in l3fwd_lpm_process_packets()
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H A Dl3fwd_lpm_altivec.h16 processx4_step1(struct rte_mbuf *pkt[FWDSTEP], in processx4_step1() argument
60 struct rte_mbuf *pkt[FWDSTEP], in processx4_step2() argument
61 uint16_t dprt[FWDSTEP]) in processx4_step2() argument
104 __vector unsigned int dip[MAX_PKT_BURST / FWDSTEP]; in l3fwd_lpm_process_packets()
105 uint32_t ipv4_flag[MAX_PKT_BURST / FWDSTEP]; in l3fwd_lpm_process_packets()
106 const int32_t k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP); in l3fwd_lpm_process_packets()
108 for (j = 0; j != k; j += FWDSTEP) in l3fwd_lpm_process_packets()
109 processx4_step1(&pkts_burst[j], &dip[j / FWDSTEP], in l3fwd_lpm_process_packets()
110 &ipv4_flag[j / FWDSTEP]); in l3fwd_lpm_process_packets()
112 for (j = 0; j != k; j += FWDSTEP) in l3fwd_lpm_process_packets()
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H A Dl3fwd_altivec.h15 #define SENDM_PORT_OVERHEAD(x) ((x) + 2 * FWDSTEP)
22 processx4_step3(struct rte_mbuf *pkt[FWDSTEP], uint16_t dst_port[FWDSTEP]) in processx4_step3()
24 __vector unsigned int te[FWDSTEP]; in processx4_step3()
25 __vector unsigned int ve[FWDSTEP]; in processx4_step3()
26 __vector unsigned int *p[FWDSTEP]; in processx4_step3()
136 k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP); in send_packets_multi()
148 for (j = FWDSTEP; j != k; j += FWDSTEP) { in send_packets_multi()
156 &dst_port[j - FWDSTEP in send_packets_multi()
19 processx4_step3(struct rte_mbuf * pkt[FWDSTEP],uint16_t dst_port[FWDSTEP]) processx4_step3() argument
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H A Dl3fwd_lpm_neon.h17 processx4_step1(struct rte_mbuf *pkt[FWDSTEP], in processx4_step1() argument
23 int32_t dst[FWDSTEP]; in processx4_step1()
57 struct rte_mbuf *pkt[FWDSTEP], in processx4_step2() argument
58 uint16_t dprt[FWDSTEP]) in processx4_step2() argument
91 const int32_t k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP); in l3fwd_lpm_process_packets()
92 const int32_t m = nb_rx % FWDSTEP; in l3fwd_lpm_process_packets()
95 for (i = 0; i < FWDSTEP; i++) { in l3fwd_lpm_process_packets()
99 for (j = 0; j != k - FWDSTEP; j += FWDSTEP) { in l3fwd_lpm_process_packets()
100 for (i = 0; i < FWDSTEP; in l3fwd_lpm_process_packets()
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H A Dl3fwd_neon.h14 #define SENDM_PORT_OVERHEAD(x) ((x) + 2 * FWDSTEP)
21 processx4_step3(struct rte_mbuf *pkt[FWDSTEP], uint16_t dst_port[FWDSTEP]) in processx4_step3()
23 uint32x4_t te[FWDSTEP]; in processx4_step3()
24 uint32x4_t ve[FWDSTEP]; in processx4_step3()
25 uint32_t *p[FWDSTEP]; in processx4_step3()
111 k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP); in send_packets_multi()
123 for (j = FWDSTEP; j != k; j += FWDSTEP) { in send_packets_multi()
130 dp2 = vld1q_u16(&dst_port[j - FWDSTEP in send_packets_multi()
18 processx4_step3(struct rte_mbuf * pkt[FWDSTEP],uint16_t dst_port[FWDSTEP]) processx4_step3() argument
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H A Dl3fwd_sse.h14 #define SENDM_PORT_OVERHEAD(x) ((x) + 2 * FWDSTEP)
21 processx4_step3(struct rte_mbuf *pkt[FWDSTEP], uint16_t dst_port[FWDSTEP]) in processx4_step3()
23 __m128i te[FWDSTEP]; in processx4_step3()
24 __m128i ve[FWDSTEP]; in processx4_step3()
25 __m128i *p[FWDSTEP]; in processx4_step3()
110 k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP); in send_packets_multi()
122 for (j = FWDSTEP; j != k; j += FWDSTEP) { in send_packets_multi()
130 &dst_port[j - FWDSTEP in send_packets_multi()
18 processx4_step3(struct rte_mbuf * pkt[FWDSTEP],uint16_t dst_port[FWDSTEP]) processx4_step3() argument
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H A Dl3fwd_common.h92 switch (n % FWDSTEP) { in send_packetsx4()
125 switch (len % FWDSTEP) { in send_packetsx4()
H A Dl3fwd_em_sequential.h150 j = RTE_ALIGN_FLOOR(vec->nb_elem, FWDSTEP); in l3fwd_em_process_event_vector()
152 for (i = 0; i != j; i += FWDSTEP) in l3fwd_em_process_event_vector()
H A Dl3fwd_em_hlm.h233 for (i = 0; i < EM_HASH_LOOKUP_COUNT && do_step3; i += FWDSTEP) in l3fwd_em_process_packets()
319 for (i = 0; i < EM_HASH_LOOKUP_COUNT; i += FWDSTEP) in l3fwd_em_process_events()
H A Dl3fwd_fib.c501 k = RTE_ALIGN_FLOOR(vec->nb_elem, FWDSTEP); in fib_process_event_vector()
503 for (i = 0; i != k; i += FWDSTEP) in fib_process_event_vector()
/dpdk/examples/ipsec-secgw/
H A Dipsec_neon.h19 processx4_step3(struct rte_mbuf *pkts[FWDSTEP], uint16_t dst_port[FWDSTEP], in processx4_step3() argument
22 uint32x4_t te[FWDSTEP]; in processx4_step3()
23 uint32x4_t ve[FWDSTEP]; in processx4_step3()
24 uint32_t *p[FWDSTEP]; in processx4_step3()
29 for (i = 0; i < FWDSTEP; i++) { in processx4_step3()
160 switch (n % FWDSTEP) { in send_packetsx4()
193 switch (len % FWDSTEP) { in send_packetsx4()
235 k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP); in send_multi_pkts()
248 for (i = FWDSTEP; i != k; i += FWDSTEP) { in send_multi_pkts()
256 dp2 = vld1q_u16(&dst_port[i - FWDSTEP + 1]); in send_multi_pkts()
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H A Dipsec_lpm_neon.h17 processx4_step1(struct rte_mbuf *pkt[FWDSTEP], int32x4_t *dip, in processx4_step1()
22 int32_t dst[FWDSTEP]; in processx4_step1()
25 for (i = 0; i < FWDSTEP; i++) { in processx4_step1()
46 struct rte_mbuf *pkt[FWDSTEP], uint16_t dprt[FWDSTEP]) in processx4_step2()
65 for (i = 0; i < FWDSTEP; i++) { in processx4_step2()
179 const int32_t k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP); in route4_pkts_neon()
180 const int32_t m = nb_rx % FWDSTEP; in route4_pkts_neon()
189 for (i = 0; i != k; i += FWDSTEP) { in route4_pkts_neon()
15 processx4_step1(struct rte_mbuf * pkt[FWDSTEP],int32x4_t * dip,uint64_t * inline_flag) processx4_step1() argument
44 processx4_step2(struct rt_ctx * rt_ctx,int32x4_t dip,uint64_t inline_flag,struct rte_mbuf * pkt[FWDSTEP],uint16_t dprt[FWDSTEP]) processx4_step2() argument
/dpdk/examples/common/sse/
H A Dport_group.h20 port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp, __m128i dp1, in port_groupx4()
24 uint16_t u16[FWDSTEP + 1]; in port_groupx4()
40 pnum->u16[FWDSTEP] = 1; in port_groupx4()
/dpdk/examples/common/neon/
H A Dport_group.h21 port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp, uint16x8_t dp1, in port_groupx4()
25 uint16_t u16[FWDSTEP + 1]; in port_groupx4()
43 pnum->u16[FWDSTEP] = 1; in port_groupx4()
/dpdk/examples/common/altivec/
H A Dport_group.h21 port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp, in port_groupx4()
26 uint16_t u16[FWDSTEP + 1]; in port_groupx4()
46 pnum->u16[FWDSTEP] = 1; in port_groupx4()
/dpdk/examples/common/
H A Dpkt_group.h10 #define FWDSTEP 4 macro
23 #define GRPSZ (1 << FWDSTEP)