Searched +full:mctp +full:- +full:controller (Results 1 – 9 of 9) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/net/mctp-i2c-controller.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: MCTP I2C transport10 - Matt Johnston <matt@codeconstruct.com.au>13 An mctp-i2c-controller defines a local MCTP endpoint on an I2C controller.14 MCTP I2C is specified by DMTF DSP0237.16 An mctp-i2c-controller must be attached to an I2C adapter which supports18 busses) are attached to the mctp-i2c-controller with a 'mctp-controller'[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 /dts-v1/;5 #include "aspeed-g6.dtsi"6 #include <dt-bindings/gpio/aspeed-gpio.h>7 #include <dt-binding[all...]
1 // SPDX-License-Identifier: GPL-2.0-only4 /dts-v1/;6 #include "aspeed-g6.dtsi"7 #include <dt-bindings/i2c/i2c.h>8 #include <dt-bindings/gpio/aspeed-gpio.h>12 compatible = "ampere,mtmitchell-bm[all...]
8 -----------------------------10 - #address-cells - should be <1>. Read more about addresses below.11 - #size-cells - should be <0>.12 - compatible - name of I2C bus controller21 -----------------------------26 - clock-frequency29 - i2c-bus31 devices and non-I2C devices, the 'i2c-bus' subnode can be used for32 populating I2C devices. If the 'i2c-bus' subnode is present, only34 '#address-cells' and '#size-cells' must be defined under this subnode[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schema[all...]
10 # https://www.iana.org/assignments/service-names-port-numbers/16 # Note that it is presently the policy of IANA to assign a single well-known47 ftp-data 20/tcp #File Transfer [Default Data]48 ftp-data 20/udp #File Transfer [Default Data]49 ftp-data 20/sctp #File Transfer [Default Data]62 nsw-fe 27/tcp #NSW User System FE63 nsw-fe 27/udp #NSW User System FE64 msg-ic[all...]
3 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec)11 * Some or all of this work - Copyright (c) 1999 - 2024, Intel Corp.28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent104 * re-exports any such software from a foreign destination, Licensee shall105 * ensure that the distribution and export/re-export of the software is in108 * any of its subsidiaries will export/re-export any technical data, process,130 * 3. Neither the names of the above-listed copyright holders nor the names181 #define ACPI_SIG_MCHI "MCHI" /* Management Controller Hos[all...]
2 * Copyright (c) 2017-2018 Cavium, Inc. 78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…116 … (0x1<<9) // Fast back-to-back transaction ena…128 … (0x1<<23) // Fast back-to-back capable. Not ap…145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…[all …]