1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _I915_DRM_H_ 28 #define _I915_DRM_H_ 29 30 /* Please note that modifications to all structs defined here are 31 * subject to backwards-compatibility constraints. 32 */ 33 34 #include "drm.h" 35 36 /* Each region is a minimum of 16k, and there are at most 255 of them. 37 */ 38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 39 * of chars for next/prev indices */ 40 #define I915_LOG_MIN_TEX_REGION_SIZE 14 41 42 typedef struct _drm_i915_init { 43 enum { 44 I915_INIT_DMA = 0x01, 45 I915_CLEANUP_DMA = 0x02, 46 I915_RESUME_DMA = 0x03, 47 48 /* Since this struct isn't versioned, just used a new 49 * 'func' code to indicate the presence of dri2 sarea 50 * info. */ 51 I915_INIT_DMA2 = 0x04 52 } func; 53 unsigned int mmio_offset; 54 int sarea_priv_offset; 55 unsigned int ring_start; 56 unsigned int ring_end; 57 unsigned int ring_size; 58 unsigned int front_offset; 59 unsigned int back_offset; 60 unsigned int depth_offset; 61 unsigned int w; 62 unsigned int h; 63 unsigned int pitch; 64 unsigned int pitch_bits; 65 unsigned int back_pitch; 66 unsigned int depth_pitch; 67 unsigned int cpp; 68 unsigned int chipset; 69 unsigned int sarea_handle; 70 } drm_i915_init_t; 71 72 typedef struct drm_i915_sarea { 73 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 74 int last_upload; /* last time texture was uploaded */ 75 int last_enqueue; /* last time a buffer was enqueued */ 76 int last_dispatch; /* age of the most recently dispatched buffer */ 77 int ctxOwner; /* last context to upload state */ 78 int texAge; 79 int pf_enabled; /* is pageflipping allowed? */ 80 int pf_active; 81 int pf_current_page; /* which buffer is being displayed? */ 82 int perf_boxes; /* performance boxes to be displayed */ 83 int width, height; /* screen size in pixels */ 84 85 drm_handle_t front_handle; 86 int front_offset; 87 int front_size; 88 89 drm_handle_t back_handle; 90 int back_offset; 91 int back_size; 92 93 drm_handle_t depth_handle; 94 int depth_offset; 95 int depth_size; 96 97 drm_handle_t tex_handle; 98 int tex_offset; 99 int tex_size; 100 int log_tex_granularity; 101 int pitch; 102 int rotation; /* 0, 90, 180 or 270 */ 103 int rotated_offset; 104 int rotated_size; 105 int rotated_pitch; 106 int virtualX, virtualY; 107 108 unsigned int front_tiled; 109 unsigned int back_tiled; 110 unsigned int depth_tiled; 111 unsigned int rotated_tiled; 112 unsigned int rotated2_tiled; 113 114 /* compat defines for the period of time when pipeA_* got renamed 115 * to planeA_*. They mean pipe, really. 116 */ 117 #define planeA_x pipeA_x 118 #define planeA_y pipeA_y 119 #define planeA_w pipeA_w 120 #define planeA_h pipeA_h 121 #define planeB_x pipeB_x 122 #define planeB_y pipeB_y 123 #define planeB_w pipeB_w 124 #define planeB_h pipeB_h 125 int pipeA_x; 126 int pipeA_y; 127 int pipeA_w; 128 int pipeA_h; 129 int pipeB_x; 130 int pipeB_y; 131 int pipeB_w; 132 int pipeB_h; 133 134 /* Triple buffering */ 135 drm_handle_t third_handle; 136 int third_offset; 137 int third_size; 138 unsigned int third_tiled; 139 140 /* buffer object handles for the static buffers. May change 141 * over the lifetime of the client, though it doesn't in our current 142 * implementation. 143 */ 144 unsigned int front_bo_handle; 145 unsigned int back_bo_handle; 146 unsigned int third_bo_handle; 147 unsigned int depth_bo_handle; 148 } drm_i915_sarea_t; 149 150 /* Driver specific fence types and classes. 151 */ 152 153 /* The only fence class we support */ 154 #define DRM_I915_FENCE_CLASS_ACCEL 0 155 /* Fence type that guarantees read-write flush */ 156 #define DRM_I915_FENCE_TYPE_RW 2 157 /* MI_FLUSH programmed just before the fence */ 158 #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000 159 160 /* Flags for perf_boxes 161 */ 162 #define I915_BOX_RING_EMPTY 0x1 163 #define I915_BOX_FLIP 0x2 164 #define I915_BOX_WAIT 0x4 165 #define I915_BOX_TEXTURE_LOAD 0x8 166 #define I915_BOX_LOST_CONTEXT 0x10 167 168 /* I915 specific ioctls 169 * The device specific ioctl range is 0x40 to 0x79. 170 */ 171 #define DRM_I915_INIT 0x00 172 #define DRM_I915_FLUSH 0x01 173 #define DRM_I915_FLIP 0x02 174 #define DRM_I915_BATCHBUFFER 0x03 175 #define DRM_I915_IRQ_EMIT 0x04 176 #define DRM_I915_IRQ_WAIT 0x05 177 #define DRM_I915_GETPARAM 0x06 178 #define DRM_I915_SETPARAM 0x07 179 #define DRM_I915_ALLOC 0x08 180 #define DRM_I915_FREE 0x09 181 #define DRM_I915_INIT_HEAP 0x0a 182 #define DRM_I915_CMDBUFFER 0x0b 183 #define DRM_I915_DESTROY_HEAP 0x0c 184 #define DRM_I915_SET_VBLANK_PIPE 0x0d 185 #define DRM_I915_GET_VBLANK_PIPE 0x0e 186 #define DRM_I915_VBLANK_SWAP 0x0f 187 #define DRM_I915_MMIO 0x10 188 #define DRM_I915_HWS_ADDR 0x11 189 #define DRM_I915_EXECBUFFER 0x12 190 #define DRM_I915_GEM_INIT 0x13 191 #define DRM_I915_GEM_EXECBUFFER 0x14 192 #define DRM_I915_GEM_PIN 0x15 193 #define DRM_I915_GEM_UNPIN 0x16 194 #define DRM_I915_GEM_BUSY 0x17 195 #define DRM_I915_GEM_THROTTLE 0x18 196 #define DRM_I915_GEM_ENTERVT 0x19 197 #define DRM_I915_GEM_LEAVEVT 0x1a 198 #define DRM_I915_GEM_CREATE 0x1b 199 #define DRM_I915_GEM_PREAD 0x1c 200 #define DRM_I915_GEM_PWRITE 0x1d 201 #define DRM_I915_GEM_MMAP 0x1e 202 #define DRM_I915_GEM_SET_DOMAIN 0x1f 203 #define DRM_I915_GEM_SW_FINISH 0x20 204 #define DRM_I915_GEM_SET_TILING 0x21 205 #define DRM_I915_GEM_GET_TILING 0x22 206 #define DRM_I915_GEM_GET_APERTURE 0x23 207 #define DRM_I915_GEM_MMAP_GTT 0x24 208 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 209 210 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 211 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 212 #define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t) 213 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 214 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 215 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 216 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 217 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 218 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 219 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 220 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 221 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 222 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 223 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 224 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 225 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 226 #define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio) 227 #define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer) 228 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 229 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 230 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 231 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 232 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 233 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 234 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 235 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 236 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 237 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 238 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 239 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 240 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 241 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 242 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 243 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 244 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 245 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 246 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 247 248 /* Asynchronous page flipping: 249 */ 250 typedef struct drm_i915_flip { 251 /* 252 * This is really talking about planes, and we could rename it 253 * except for the fact that some of the duplicated i915_drm.h files 254 * out there check for HAVE_I915_FLIP and so might pick up this 255 * version. 256 */ 257 /* XXXMRG: make this unsigned? */ 258 int pipes; 259 } drm_i915_flip_t; 260 261 /* Allow drivers to submit batchbuffers directly to hardware, relying 262 * on the security mechanisms provided by hardware. 263 */ 264 typedef struct drm_i915_batchbuffer { 265 int start; /* agp offset */ 266 int used; /* nr bytes in use */ 267 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 268 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 269 int num_cliprects; /* mulitpass with multiple cliprects? */ 270 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 271 } drm_i915_batchbuffer_t; 272 273 /* As above, but pass a pointer to userspace buffer which can be 274 * validated by the kernel prior to sending to hardware. 275 */ 276 typedef struct _drm_i915_cmdbuffer { 277 char __user *buf; /* pointer to userspace command buffer */ 278 int sz; /* nr bytes in buf */ 279 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 280 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 281 int num_cliprects; /* mulitpass with multiple cliprects? */ 282 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 283 } drm_i915_cmdbuffer_t; 284 285 /* Userspace can request & wait on irq's: 286 */ 287 typedef struct drm_i915_irq_emit { 288 int __user *irq_seq; 289 } drm_i915_irq_emit_t; 290 291 typedef struct drm_i915_irq_wait { 292 int irq_seq; 293 } drm_i915_irq_wait_t; 294 295 /* Ioctl to query kernel params: 296 */ 297 #define I915_PARAM_IRQ_ACTIVE 1 298 #define I915_PARAM_ALLOW_BATCHBUFFER 2 299 #define I915_PARAM_LAST_DISPATCH 3 300 #define I915_PARAM_CHIPSET_ID 4 301 #define I915_PARAM_HAS_GEM 5 302 #define I915_PARAM_NUM_FENCES_AVAIL 6 303 304 typedef struct drm_i915_getparam { 305 int param; 306 int __user *value; 307 } drm_i915_getparam_t; 308 309 /* Ioctl to set kernel params: 310 */ 311 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 312 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 313 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 314 #define I915_SETPARAM_NUM_USED_FENCES 4 315 316 typedef struct drm_i915_setparam { 317 int param; 318 int value; 319 } drm_i915_setparam_t; 320 321 /* A memory manager for regions of shared memory: 322 */ 323 #define I915_MEM_REGION_AGP 1 324 325 typedef struct drm_i915_mem_alloc { 326 int region; 327 int alignment; 328 int size; 329 int __user *region_offset; /* offset from start of fb or agp */ 330 } drm_i915_mem_alloc_t; 331 332 typedef struct drm_i915_mem_free { 333 int region; 334 int region_offset; 335 } drm_i915_mem_free_t; 336 337 typedef struct drm_i915_mem_init_heap { 338 int region; 339 int size; 340 int start; 341 } drm_i915_mem_init_heap_t; 342 343 /* Allow memory manager to be torn down and re-initialized (eg on 344 * rotate): 345 */ 346 typedef struct drm_i915_mem_destroy_heap { 347 int region; 348 } drm_i915_mem_destroy_heap_t; 349 350 /* Allow X server to configure which pipes to monitor for vblank signals 351 */ 352 #define DRM_I915_VBLANK_PIPE_A 1 353 #define DRM_I915_VBLANK_PIPE_B 2 354 355 typedef struct drm_i915_vblank_pipe { 356 int pipe; 357 } drm_i915_vblank_pipe_t; 358 359 /* Schedule buffer swap at given vertical blank: 360 */ 361 typedef struct drm_i915_vblank_swap { 362 drm_drawable_t drawable; 363 enum drm_vblank_seq_type seqtype; 364 unsigned int sequence; 365 } drm_i915_vblank_swap_t; 366 367 #define I915_MMIO_READ 0 368 #define I915_MMIO_WRITE 1 369 370 #define I915_MMIO_MAY_READ 0x1 371 #define I915_MMIO_MAY_WRITE 0x2 372 373 #define MMIO_REGS_IA_PRIMATIVES_COUNT 0 374 #define MMIO_REGS_IA_VERTICES_COUNT 1 375 #define MMIO_REGS_VS_INVOCATION_COUNT 2 376 #define MMIO_REGS_GS_PRIMITIVES_COUNT 3 377 #define MMIO_REGS_GS_INVOCATION_COUNT 4 378 #define MMIO_REGS_CL_PRIMITIVES_COUNT 5 379 #define MMIO_REGS_CL_INVOCATION_COUNT 6 380 #define MMIO_REGS_PS_INVOCATION_COUNT 7 381 #define MMIO_REGS_PS_DEPTH_COUNT 8 382 383 typedef struct drm_i915_mmio_entry { 384 unsigned int flag; 385 unsigned int offset; 386 unsigned int size; 387 } drm_i915_mmio_entry_t; 388 389 typedef struct drm_i915_mmio { 390 unsigned int read_write:1; 391 unsigned int reg:31; 392 void __user *data; 393 } drm_i915_mmio_t; 394 395 typedef struct drm_i915_hws_addr { 396 uint64_t addr; 397 } drm_i915_hws_addr_t; 398 399 /* 400 * Relocation header is 4 uint32_ts 401 * 0 - 32 bit reloc count 402 * 1 - 32-bit relocation type 403 * 2-3 - 64-bit user buffer handle ptr for another list of relocs. 404 */ 405 #define I915_RELOC_HEADER 4 406 407 /* 408 * type 0 relocation has 4-uint32_t stride 409 * 0 - offset into buffer 410 * 1 - delta to add in 411 * 2 - buffer handle 412 * 3 - reserved (for optimisations later). 413 */ 414 /* 415 * type 1 relocation has 4-uint32_t stride. 416 * Hangs off the first item in the op list. 417 * Performed after all valiations are done. 418 * Try to group relocs into the same relocatee together for 419 * performance reasons. 420 * 0 - offset into buffer 421 * 1 - delta to add in 422 * 2 - buffer index in op list. 423 * 3 - relocatee index in op list. 424 */ 425 #define I915_RELOC_TYPE_0 0 426 #define I915_RELOC0_STRIDE 4 427 #define I915_RELOC_TYPE_1 1 428 #define I915_RELOC1_STRIDE 4 429 430 431 struct drm_i915_op_arg { 432 uint64_t next; 433 uint64_t reloc_ptr; 434 int handled; 435 unsigned int pad64; 436 union { 437 struct drm_bo_op_req req; 438 struct drm_bo_arg_rep rep; 439 } d; 440 441 }; 442 443 struct drm_i915_execbuffer { 444 uint64_t ops_list; 445 uint32_t num_buffers; 446 struct drm_i915_batchbuffer batch; 447 drm_context_t context; /* for lockless use in the future */ 448 struct drm_fence_arg fence_arg; 449 }; 450 451 struct drm_i915_gem_init { 452 /** 453 * Beginning offset in the GTT to be managed by the DRM memory 454 * manager. 455 */ 456 uint64_t gtt_start; 457 /** 458 * Ending offset in the GTT to be managed by the DRM memory 459 * manager. 460 */ 461 uint64_t gtt_end; 462 }; 463 464 struct drm_i915_gem_create { 465 /** 466 * Requested size for the object. 467 * 468 * The (page-aligned) allocated size for the object will be returned. 469 */ 470 uint64_t size; 471 /** 472 * Returned handle for the object. 473 * 474 * Object handles are nonzero. 475 */ 476 uint32_t handle; 477 uint32_t pad; 478 }; 479 480 struct drm_i915_gem_pread { 481 /** Handle for the object being read. */ 482 uint32_t handle; 483 uint32_t pad; 484 /** Offset into the object to read from */ 485 uint64_t offset; 486 /** Length of data to read */ 487 uint64_t size; 488 /** 489 * Pointer to write the data into. 490 * 491 * This is a fixed-size type for 32/64 compatibility. 492 */ 493 uint64_t data_ptr; 494 }; 495 496 struct drm_i915_gem_pwrite { 497 /** Handle for the object being written to. */ 498 uint32_t handle; 499 uint32_t pad; 500 /** Offset into the object to write to */ 501 uint64_t offset; 502 /** Length of data to write */ 503 uint64_t size; 504 /** 505 * Pointer to read the data from. 506 * 507 * This is a fixed-size type for 32/64 compatibility. 508 */ 509 uint64_t data_ptr; 510 }; 511 512 struct drm_i915_gem_mmap { 513 /** Handle for the object being mapped. */ 514 uint32_t handle; 515 uint32_t pad; 516 /** Offset in the object to map. */ 517 uint64_t offset; 518 /** 519 * Length of data to map. 520 * 521 * The value will be page-aligned. 522 */ 523 uint64_t size; 524 /** 525 * Returned pointer the data was mapped at. 526 * 527 * This is a fixed-size type for 32/64 compatibility. 528 */ 529 uint64_t addr_ptr; 530 }; 531 532 struct drm_i915_gem_mmap_gtt { 533 /** Handle for the object being mapped. */ 534 uint32_t handle; 535 uint32_t pad; 536 /** 537 * Fake offset to use for subsequent mmap call 538 * 539 * This is a fixed-size type for 32/64 compatibility. 540 */ 541 uint64_t offset; 542 }; 543 544 struct drm_i915_gem_set_domain { 545 /** Handle for the object */ 546 uint32_t handle; 547 548 /** New read domains */ 549 uint32_t read_domains; 550 551 /** New write domain */ 552 uint32_t write_domain; 553 }; 554 555 struct drm_i915_gem_sw_finish { 556 /** Handle for the object */ 557 uint32_t handle; 558 }; 559 560 struct drm_i915_gem_relocation_entry { 561 /** 562 * Handle of the buffer being pointed to by this relocation entry. 563 * 564 * It's appealing to make this be an index into the mm_validate_entry 565 * list to refer to the buffer, but this allows the driver to create 566 * a relocation list for state buffers and not re-write it per 567 * exec using the buffer. 568 */ 569 uint32_t target_handle; 570 571 /** 572 * Value to be added to the offset of the target buffer to make up 573 * the relocation entry. 574 */ 575 uint32_t delta; 576 577 /** Offset in the buffer the relocation entry will be written into */ 578 uint64_t offset; 579 580 /** 581 * Offset value of the target buffer that the relocation entry was last 582 * written as. 583 * 584 * If the buffer has the same offset as last time, we can skip syncing 585 * and writing the relocation. This value is written back out by 586 * the execbuffer ioctl when the relocation is written. 587 */ 588 uint64_t presumed_offset; 589 590 /** 591 * Target memory domains read by this operation. 592 */ 593 uint32_t read_domains; 594 595 /** 596 * Target memory domains written by this operation. 597 * 598 * Note that only one domain may be written by the whole 599 * execbuffer operation, so that where there are conflicts, 600 * the application will get -EINVAL back. 601 */ 602 uint32_t write_domain; 603 }; 604 605 /** @{ 606 * Intel memory domains 607 * 608 * Most of these just align with the various caches in 609 * the system and are used to flush and invalidate as 610 * objects end up cached in different domains. 611 */ 612 /** CPU cache */ 613 #define I915_GEM_DOMAIN_CPU 0x00000001 614 /** Render cache, used by 2D and 3D drawing */ 615 #define I915_GEM_DOMAIN_RENDER 0x00000002 616 /** Sampler cache, used by texture engine */ 617 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 618 /** Command queue, used to load batch buffers */ 619 #define I915_GEM_DOMAIN_COMMAND 0x00000008 620 /** Instruction cache, used by shader programs */ 621 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 622 /** Vertex address cache */ 623 #define I915_GEM_DOMAIN_VERTEX 0x00000020 624 /** GTT domain - aperture and scanout */ 625 #define I915_GEM_DOMAIN_GTT 0x00000040 626 /** @} */ 627 628 struct drm_i915_gem_exec_object { 629 /** 630 * User's handle for a buffer to be bound into the GTT for this 631 * operation. 632 */ 633 uint32_t handle; 634 635 /** Number of relocations to be performed on this buffer */ 636 uint32_t relocation_count; 637 /** 638 * Pointer to array of struct drm_i915_gem_relocation_entry containing 639 * the relocations to be performed in this buffer. 640 */ 641 uint64_t relocs_ptr; 642 643 /** Required alignment in graphics aperture */ 644 uint64_t alignment; 645 646 /** 647 * Returned value of the updated offset of the object, for future 648 * presumed_offset writes. 649 */ 650 uint64_t offset; 651 }; 652 653 struct drm_i915_gem_execbuffer { 654 /** 655 * List of buffers to be validated with their relocations to be 656 * performend on them. 657 * 658 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 659 * 660 * These buffers must be listed in an order such that all relocations 661 * a buffer is performing refer to buffers that have already appeared 662 * in the validate list. 663 */ 664 uint64_t buffers_ptr; 665 uint32_t buffer_count; 666 667 /** Offset in the batchbuffer to start execution from. */ 668 uint32_t batch_start_offset; 669 /** Bytes used in batchbuffer from batch_start_offset */ 670 uint32_t batch_len; 671 uint32_t DR1; 672 uint32_t DR4; 673 uint32_t num_cliprects; 674 /** This is a struct drm_clip_rect *cliprects */ 675 uint64_t cliprects_ptr; 676 }; 677 678 struct drm_i915_gem_pin { 679 /** Handle of the buffer to be pinned. */ 680 uint32_t handle; 681 uint32_t pad; 682 683 /** alignment required within the aperture */ 684 uint64_t alignment; 685 686 /** Returned GTT offset of the buffer. */ 687 uint64_t offset; 688 }; 689 690 struct drm_i915_gem_unpin { 691 /** Handle of the buffer to be unpinned. */ 692 uint32_t handle; 693 uint32_t pad; 694 }; 695 696 struct drm_i915_gem_busy { 697 /** Handle of the buffer to check for busy */ 698 uint32_t handle; 699 700 /** Return busy status (1 if busy, 0 if idle) */ 701 uint32_t busy; 702 }; 703 704 #define I915_TILING_NONE 0 705 #define I915_TILING_X 1 706 #define I915_TILING_Y 2 707 708 #define I915_BIT_6_SWIZZLE_NONE 0 709 #define I915_BIT_6_SWIZZLE_9 1 710 #define I915_BIT_6_SWIZZLE_9_10 2 711 #define I915_BIT_6_SWIZZLE_9_11 3 712 #define I915_BIT_6_SWIZZLE_9_10_11 4 713 /* Not seen by userland */ 714 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 715 716 struct drm_i915_gem_set_tiling { 717 /** Handle of the buffer to have its tiling state updated */ 718 uint32_t handle; 719 720 /** 721 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 722 * I915_TILING_Y). 723 * 724 * This value is to be set on request, and will be updated by the 725 * kernel on successful return with the actual chosen tiling layout. 726 * 727 * The tiling mode may be demoted to I915_TILING_NONE when the system 728 * has bit 6 swizzling that can't be managed correctly by GEM. 729 * 730 * Buffer contents become undefined when changing tiling_mode. 731 */ 732 uint32_t tiling_mode; 733 734 /** 735 * Stride in bytes for the object when in I915_TILING_X or 736 * I915_TILING_Y. 737 */ 738 uint32_t stride; 739 740 /** 741 * Returned address bit 6 swizzling required for CPU access through 742 * mmap mapping. 743 */ 744 uint32_t swizzle_mode; 745 }; 746 747 struct drm_i915_gem_get_tiling { 748 /** Handle of the buffer to get tiling state for. */ 749 uint32_t handle; 750 751 /** 752 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 753 * I915_TILING_Y). 754 */ 755 uint32_t tiling_mode; 756 757 /** 758 * Returned address bit 6 swizzling required for CPU access through 759 * mmap mapping. 760 */ 761 uint32_t swizzle_mode; 762 }; 763 764 struct drm_i915_gem_get_aperture { 765 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 766 uint64_t aper_size; 767 768 /** 769 * Available space in the aperture used by i915_gem_execbuffer, in 770 * bytes 771 */ 772 uint64_t aper_available_size; 773 }; 774 775 struct drm_i915_get_pipe_from_crtc_id { 776 /** ID of CRTC being requested **/ 777 uint32_t crtc_id; 778 779 /** pipe of requested CRTC **/ 780 uint32_t pipe; 781 }; 782 783 #endif /* _I915_DRM_H_ */ 784