Searched defs:Orders (Results 1 – 5 of 5) sorted by relevance
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 786 SmallVectorImpl<std::pair<unsigned, MachineInstr *>> &Orders, in ProcessSourceNode() argument
856 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
738 ProcessSDDbgValues(SDNode * N,SelectionDAG * DAG,InstrEmitter & Emitter,SmallVectorImpl<std::pair<unsigned,MachineInstr * >> & Orders,DenseMap<SDValue,Register> & VRBaseMap,unsigned Order) ProcessSDDbgValues() argument
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | InlineSpiller.cpp | 1407 getVisitOrders(MachineBasicBlock * Root,SmallPtrSet<MachineInstr *,16> & Spills,SmallVectorImpl<MachineDomTreeNode * > & Orders,SmallVectorImpl<MachineInstr * > & SpillsToRm,DenseMap<MachineDomTreeNode *,unsigned> & SpillsToKeep,DenseMap<MachineDomTreeNode *,MachineInstr * > & SpillBBToSpill) getVisitOrders() argument
1495 SmallVector<MachineDomTreeNode *, 32> Orders; runHoistSpills() local
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| /llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | ConstantHoisting.cpp | 259 while (Idx != Orders.size()) { in findBestInsertionSet() local
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| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.h | 317 std::vector<SmallVector<const Record *, 16>> Orders; variable
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| /llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 4738 llvm::AtomicOrdering Orders[5] = { EmitBuiltinExpr() local
4803 llvm::AtomicOrdering Orders[3] = { EmitBuiltinExpr() local
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