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Searched defs:ItinData (Results 1 – 10 of 10) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h34 PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, in PPCDispatchGroupSBHazardRecognizer()
H A DPPCInstrInfo.h319 int getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
H A DPPCInstrInfo.cpp136 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
166 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DScoreboardHazardRecognizer.h94 const InstrItineraryData *ItinData; variable
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp1089 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
1105 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
1120 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps()
1151 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
1165 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries(); in hasLowDefLatency() local
1257 int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
1270 const InstrItineraryData *ItinData, const MachineInstr &DefMI) const { in computeDefOperandLatency() argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3425 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, in getNumMicroOpsSwiftLdSt()
3727 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps()
3841 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, in getVLDMDefCycle()
3882 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, in getLDMDefCycle()
3917 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, in getVSTMUseCycle()
3957 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, in getSTMUseCycle()
3986 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
4330 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
4367 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatencyImpl()
4427 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
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/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp295 Record *ItinData, in FormItineraryStageString()
338 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, in FormItineraryOperandCycleString()
355 Record *ItinData, in FormItineraryBypassString()
457 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1882 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
4201 const InstrItineraryData *ItinData, const MachineInstr &MI) const { in getInstrTimingClassLatency() argument
4220 int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp987 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
H A DSIInstrInfo.cpp7818 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()