Searched refs:BAR (Results 1 – 4 of 4) sorted by relevance
288 return dev->header->zero.BAR[index] & ~0xf; in vmd_get_base_addr() 321 bar_value = dev->header->zero.BAR[i]; in vmd_assign_base_addrs() 322 dev->header->zero.BAR[i] = ~(0U); in vmd_assign_base_addrs() 323 dev->bar[i].size = dev->header->zero.BAR[i]; in vmd_assign_base_addrs() 324 dev->header->zero.BAR[i] = bar_value; in vmd_assign_base_addrs() 327 dev->header->zero.BAR[i] & 1) { in vmd_assign_base_addrs() 340 dev->header->zero.BAR[i] = (uint32_t)dev->bar[i].start; in vmd_assign_base_addrs() 350 mem_limit = BRIDGE_BASEREG(dev->header->zero.BAR[i]) + in vmd_assign_base_addrs() 353 mem_base = BRIDGE_BASEREG(dev->header->zero.BAR[i]); in vmd_assign_base_addrs() 361 dev->header->zero.BAR[ in vmd_assign_base_addrs() [all...]
138 uint32_t BAR[6]; member161 uint32_t BAR[2]; member
124 BAR)129 BAR)
48 [PCI BAR](https://en.wikipedia.org/wiki/PCI_configuration_space) for the device51 nvme, for instance, maps the BAR for the NVMe device and then follows along