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Searched refs:createVirtualRegister (Results 1 – 25 of 164) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp185 Register MoveReg = MRI.createVirtualRegister(&PPC::VSFRCRegClass); in selectIntToFP()
212 Register CopyReg = MRI.createVirtualRegister(&PPC::VSFRCRegClass); in selectFPToInt()
215 Register ConvReg = MRI.createVirtualRegister(&PPC::VSFRCRegClass); in selectFPToInt()
244 MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank)); in selectZExt()
249 MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank)); in selectZExt()
316 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect()
333 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect()
364 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect()
392 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect()
408 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp168 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); in materialize32BitImm()
322 Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); in select()
373 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
381 Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
389 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
401 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
480 Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
483 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
512 Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); in select()
598 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
[all …]
H A DMipsISelLowering.cpp1255 Register VReg = MF.getRegInfo().createVirtualRegister(RC); in addLiveIn()
1556 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); in emitAtomicBinary()
1595 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr)); in emitAtomicBinary()
1596 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr)); in emitAtomicBinary()
1610 RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); in emitAtomicBinary()
1639 Register ScrReg = RegInfo.createVirtualRegister(RC); in emitSignExtendToI32InReg()
1668 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicBinaryPartword()
1669 Register ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1670 Register Mask = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1671 Register Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
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H A DMipsMachineFunction.cpp57 MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF)); in getGlobalBaseReg()
83 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
84 Register V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
H A DMips16ISelDAGToDAG.cpp78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
79 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
80 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
H A DMipsSEISelLowering.cpp3058 Register VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3064 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3127 Register RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3133 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3174 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); in emitCOPY_FW()
3181 Register Wt = RegInfo.createVirtualRegister( in emitCOPY_FW()
3218 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); in emitCOPY_FD()
3244 Register Wt = RegInfo.createVirtualRegister( in emitINSERT_FW()
3280 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); in emitINSERT_FD()
3366 Register Wt = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
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H A DMipsSEFrameLowering.cpp174 Register VR = MRI.createVirtualRegister(RC); in expandLoadCCond()
189 Register VR = MRI.createVirtualRegister(RC); in expandStoreCCond()
207 Register VR0 = MRI.createVirtualRegister(RC); in expandLoadACC()
208 Register VR1 = MRI.createVirtualRegister(RC); in expandLoadACC()
232 Register VR0 = MRI.createVirtualRegister(RC); in expandStoreACC()
233 Register VR1 = MRI.createVirtualRegister(RC); in expandStoreACC()
265 Register VR0 = MRI.createVirtualRegister(RC); in expandCopyACC()
266 Register VR1 = MRI.createVirtualRegister(RC); in expandCopyACC()
541 Register VR = MF.getRegInfo().createVirtualRegister(RC); in emitPrologue()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp65 Register AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandStore()
90 Register Ra = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
91 Register Rb = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
118 Register R = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTTZ()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp448 PS->PoisonReg = MRI->createVirtualRegister(PS->RC); in runOnMachineFunction()
481 PS->InitialReg = MRI->createVirtualRegister(PS->RC); in runOnMachineFunction()
482 Register PredStateSubReg = MRI->createVirtualRegister(&X86::GR32RegClass); in runOnMachineFunction()
755 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC); in tracePredStateThroughCFG()
910 Register Reg = MRI->createVirtualRegister(UnfoldedRC); in unfoldCallAndJumpLoads()
968 TargetAddrSSA.Initialize(MRI->createVirtualRegister(&X86::GR64RegClass)); in tracePredStateThroughIndirectBranches()
1110 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches()
1161 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches()
1183 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC); in tracePredStateThroughIndirectBranches()
1507 Register Reg = MRI->createVirtualRegister(&X86::GR32RegClass); in saveEFLAGS()
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H A DX86FastPreTileConfig.cpp169 Register Zmm = MRI->createVirtualRegister(&X86::VR512RegClass); in InitializeTileConfigStackSpace()
174 Register Ymm = MRI->createVirtualRegister(&X86::VR256RegClass); in InitializeTileConfigStackSpace()
184 Register Xmm = MRI->createVirtualRegister(&X86::VR128RegClass); in InitializeTileConfigStackSpace()
236 TileReg = MRI->createVirtualRegister(&RC); in reload()
241 Register StrideReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in reload()
330 Register StackAddrReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in convertPHI()
333 Register RowReg = MRI->createVirtualRegister(&X86::GR16RegClass); in convertPHI()
336 Register ColReg = MRI->createVirtualRegister(&X86::GR16RegClass); in convertPHI()
400 MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in convertPHI()
410 Register StrideReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in convertPHI()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp278 SPReg = MRI.createVirtualRegister(PtrRC); in emitPrologue()
288 Register BasePtr = MRI.createVirtualRegister(PtrRC); in emitPrologue()
295 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue()
303 Register BitmaskReg = MRI.createVirtualRegister(PtrRC); in emitPrologue()
347 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
353 SPReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
H A DWebAssemblyPeephole.cpp67 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop()
100 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp1142 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1155 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1169 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1185 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1199 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1211 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1212 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC()); in insertVectorSelect()
1229 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1230 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC()); in insertVectorSelect()
1260 Register Reg = MRI.createVirtualRegister(RI.getBoolRC()); in insertEQ()
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H A DAMDGPUInstructionSelector.cpp155 Register MaskedReg = MRI->createVirtualRegister(SrcRC); in selectCOPY()
243 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64()
340 Register UnusedCarry = MRI->createVirtualRegister(TRI.getWaveMaskRegClass()); in selectG_ADD_SUB()
363 Register DstLo = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB()
364 Register DstHi = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB()
375 Register CarryReg = MRI->createVirtualRegister(CarryRC); in selectG_ADD_SUB()
382 .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead) in selectG_ADD_SUB()
743 Register TmpReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectG_BUILD_VECTOR()
933 Register InterpMov = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectInterpP1F16()
1654 Register M0Base = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectDSGWSIntrinsic()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp37 auto VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVReg()
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVRegDefAt()
133 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in createEntriesInEntryBlock()
242 UpwardsUse ? UUseVReg : MF->getRegInfo().createVirtualRegister(RC); in propagateVRegs()
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.cpp200 ? MRI.createVirtualRegister(&CSKY::GPRRegClass) in eliminateFrameIndex()
201 : MRI.createVirtualRegister(&CSKY::mGPRRegClass); in eliminateFrameIndex()
221 NewReg = MRI.createVirtualRegister(&CSKY::GPRRegClass); in eliminateFrameIndex()
225 NewReg = MRI.createVirtualRegister(&CSKY::mGPRRegClass); in eliminateFrameIndex()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp759 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
848 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca()
856 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca()
865 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
873 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
969 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
981 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
1014 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
1026 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
1058 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRBitSpilling()
[all …]
H A DPPCVSXCopy.cpp105 Register NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
127 Register NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
H A DPPCCTRLoops.cpp254 MRI->createVirtualRegister(Is64Bit ? &PPC::G8RC_and_G8RC_NOX0RegClass in expandNormalLoops()
266 MRI->createVirtualRegister(Is64Bit ? &PPC::G8RC_and_G8RC_NOX0RegClass in expandNormalLoops()
299 Register CMPDef = MRI->createVirtualRegister(&PPC::CRRCRegClass); in expandNormalLoops()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp82 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass); in visitMBB()
92 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass); in visitMBB()
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.cpp155 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass); in eliminateFrameIndex()
174 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass); in eliminateFrameIndex()
187 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass); in eliminateFrameIndex()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp418 MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass); in createDupLane()
433 Register Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
447 Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass); in createRegSequence()
465 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass); in createVExt()
477 Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass); in createInsertSubreg()
493 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass); in createImplicitDef()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp71 Register ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genElemLoad()
90 Register IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genElemLoad()
124 Register AddrR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in runOnMachineFunction()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp191 ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in adjustReg()
242 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in adjustReg()
288 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVSPILL()
299 Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVSPILL()
357 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVRELOAD()
368 Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVRELOAD()
445 DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in eliminateFrameIndex()
585 Register BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass); in materializeFrameBaseRegister()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp343 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
349 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
357 Register Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()

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