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Searched refs:createReg (Results 1 – 25 of 88) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp580 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
594 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
596 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
632 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
635 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
659 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
661 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
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/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp114 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRRegisterClass()
124 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo])); in DecodeFPR32RegisterClass()
134 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo])); in DecodesFPR32RegisterClass()
144 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodesFPR64RegisterClass()
154 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodesFPR64_VRegisterClass()
164 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodeFPR64RegisterClass()
176 Inst.addOperand(MCOperand::createReg(FPR128DecoderTable[RegNo])); in DecodesFPR128RegisterClass()
186 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodesGPRRegisterClass()
196 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodemGPRRegisterClass()
208 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRSPRegisterClass()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp74 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR8RegisterClass()
85 Inst.addOperand(MCOperand::createReg(Register)); in DecodeLD8RegisterClass()
192 Inst.addOperand(MCOperand::createReg(AVR::R31R30)); in decodeFLPMX()
264 MCOperand::createReg((Insn & 0x40) ? AVR::R29R28 : AVR::R31R30)); in decodeMemri()
302 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
303 Inst.addOperand(MCOperand::createReg(RegBase)); in decodeLoadStore()
307 Inst.addOperand(MCOperand::createReg(RegBase)); in decodeLoadStore()
309 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
355 Inst.addOperand(MCOperand::createReg(RegBase)); in decodeLoadStore()
356 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp87 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
270 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1])); in decodeVSRpEvenOperands()
294 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
301 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
306 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
323 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
325 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
328 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
345 Inst.addOperand(MCOperand::createReg(RRegs[Base])); in decodeMemRIHashOperands()
361 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIX16Operands()
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/openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVMCInstLower.cpp36 MCOp = MCOperand::createReg(FuncReg); in lower()
40 MCOp = MCOperand::createReg(MAI->getOrCreateMBBRegister(*MO.getMBB())); in lower()
44 MCOp = MCOperand::createReg(NewReg.isValid() ? NewReg : MO.getReg()); in lower()
50 MCOp = MCOperand::createReg(Reg); in lower()
H A DSPIRVAsmPrinter.cpp141 LabelInst.addOperand(MCOperand::createReg(MAI->getOrCreateMBBRegister(MBB))); in emitOpLabel()
271 Inst.addOperand(MCOperand::createReg(Reg)); in outputOpExtInstImports()
317 TmpInst.addOperand(MCOperand::createReg(Reg)); in outputEntryPoints()
399 Inst.addOperand(MCOperand::createReg(FuncReg)); in addOpsFromMDNode()
409 Inst.addOperand(MCOperand::createReg(Reg)); in outputExecutionModeFromMDNode()
443 Inst.addOperand(MCOperand::createReg(FReg)); in outputExecutionMode()
454 Inst.addOperand(MCOperand::createReg(FReg)); in outputExecutionMode()
488 Inst.addOperand(MCOperand::createReg(Reg)); in outputAnnotations()
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/Disassembler/
H A DLoongArchDisassembler.cpp63 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo)); in DecodeGPRRegisterClass()
72 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo)); in DecodeFPR32RegisterClass()
81 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo)); in DecodeFPR64RegisterClass()
90 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo)); in DecodeCFRRegisterClass()
99 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo)); in DecodeFCSRRegisterClass()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp72 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
83 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass()
94 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
105 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
116 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
127 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
158 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass()
169 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRPF64RegisterClass()
180 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRRegisterClass()
200 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRM2RegisterClass()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp87 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
316 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
327 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
329 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
339 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr20Operand()
341 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr20Operand()
351 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len4Operand()
363 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len8Operand()
375 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDRAddr12Operand()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstrInfo.cpp40 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
43 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
46 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
H A DARMAsmPrinter.cpp1495 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in emitInstruction()
1516 TmpInst.addOperand(MCOperand::createReg(0)); in emitInstruction()
1518 TmpInst.addOperand(MCOperand::createReg(0)); in emitInstruction()
1527 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in emitInstruction()
1528 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg())); in emitInstruction()
1548 TmpInst.addOperand(MCOperand::createReg(0)); in emitInstruction()
1550 TmpInst.addOperand(MCOperand::createReg(0)); in emitInstruction()
1853 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in emitInstruction()
1854 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in emitInstruction()
1857 TmpInst.addOperand(MCOperand::createReg(0)); in emitInstruction()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp151 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeIntRegsRegisterClass()
175 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRegsRegisterClass()
185 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeDFPRegsRegisterClass()
198 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeQFPRegsRegisterClass()
208 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeCoprocRegsRegisterClass()
217 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); in DecodeFCCRegsRegisterClass()
226 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); in DecodeASRRegsRegisterClass()
235 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); in DecodePRRegsRegisterClass()
251 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeIntPairRegisterClass()
262 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeCoprocPairRegisterClass()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
188 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
201 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
219 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
220 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
229 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
237 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX()
238 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
239 TmpInst.addOperand(MCOperand::createReg(Reg2)); in emitRRRX()
257 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRIII()
[all …]
H A DMipsNaClELFStreamer.cpp105 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
106 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
107 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp1797 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
1825 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateSrcIndex()
1829 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
1850 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateDstIndex()
1935 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
1938 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
1941 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
1955 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateImmediate()
1988 mcInst.addOperand(MCOperand::createReg(X86::x)); break; in translateRMRegister()
2035 baseReg = MCOperand::createReg(X86::x); break; in translateRMMemory()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp344 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA)); in getInstruction()
347 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0)); in getInstruction()
350 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0)); in getInstruction()
425 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR128RegisterClass()
445 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR64RegisterClass()
457 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR32RegisterClass()
469 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR16RegisterClass()
481 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR8RegisterClass()
494 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64commonRegisterClass()
506 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64RegisterClass()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h537 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
545 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
554 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR16orGR32orGR64Operands()
588 Inst.addOperand(MCOperand::createReg(Reg)); in addMaskPairOperands()
594 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands()
596 Inst.addOperand(MCOperand::createReg(getMemDefaultBaseReg())); in addMemOperands()
598 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands()
600 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands()
614 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addSrcIdxOperands()
615 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addSrcIdxOperands()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2487 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
2494 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredNOperands()
2495 Inst.addOperand(MCOperand::createReg(0)); in addVPTPredNOperands()
2513 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredROperands()
2548 Inst.addOperand(MCOperand::createReg(getReg())); in addCCOutOperands()
2553 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
2560 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); in addRegShiftedRegOperands()
2561 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
2570 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); in addRegShiftedImmOperands()
2587 Inst.addOperand(MCOperand::createReg(Reg)); in addRegListOperands()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVMCInstLower.cpp100 MCOp = MCOperand::createReg(MO.getReg()); in lowerRISCVMachineOperandToMCOperand()
198 MCOp = MCOperand::createReg(Reg); in lowerRISCVVMachineInstrToMCInst()
211 OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister)); in lowerRISCVVMachineInstrToMCInst()
247 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst()
253 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst()
/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
180 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
195 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
206 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp188 MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); in lowerGETGOTAndEmitMCInsts()
205 MCOperand RegGOT = MCOperand::createReg(VE::SX15); // GOT in lowerGETGOTAndEmitMCInsts()
206 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT in lowerGETGOTAndEmitMCInsts()
227 MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); in lowerGETFunPLTAndEmitMCInsts()
254 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT in lowerGETFunPLTAndEmitMCInsts()
295 MCOperand RegLR = MCOperand::createReg(VE::SX10); // LR in lowerGETTLSAddrAndEmitMCInsts()
296 MCOperand RegS0 = MCOperand::createReg(VE::SX0); // S0 in lowerGETTLSAddrAndEmitMCInsts()
297 MCOperand RegS12 = MCOperand::createReg(VE::SX12); // S12 in lowerGETTLSAddrAndEmitMCInsts()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp1182 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg()); in LowerSTATEPOINT()
1222 MI.addOperand(MCOperand::createReg(DefRegister)); in LowerFAULTING_OP()
1249 MOVI.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1258 FMov.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1259 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in emitFMov0()
1263 FMov.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1264 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in emitFMov0()
1268 FMov.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1269 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in emitFMov0()
1344 MovZ.addOperand(MCOperand::createReg(DestReg)); in emitInstruction()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp108 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
123 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
134 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeMemoryOpValue()
215 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp456 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
461 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
466 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
471 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
476 Inst.addOperand(MCOperand::createReg(XRegs[getG8pReg()])); in addRegG8pRCOperands()
495 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
500 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
505 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); in addRegVFRCOperands()
510 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
515 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp894 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
899 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
992 MI.insert(CCI, MCOperand::createReg(0)); in AddThumbPredicate()
994 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
1010 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); in AddThumbPredicate()
1012 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); in AddThumbPredicate()
1014 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); in AddThumbPredicate()
1300 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass()
1314 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCLRMGPRRegisterClass()
1351 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
[all …]

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