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Searched refs:TheDef (Results 1 – 25 of 41) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/utils/TableGen/
H A DAsmWriterInst.cpp95 CGI.TheDef->getLoc(), in AsmWriterInst()
97 CGI.TheDef->getName() + "'!"); in AsmWriterInst()
135 CGI.TheDef->getLoc(), in AsmWriterInst()
137 CGI.TheDef->getName() + "'"); in AsmWriterInst()
144 CGI.TheDef->getLoc(), in AsmWriterInst()
146 CGI.TheDef->getName() + "'"); in AsmWriterInst()
153 PrintFatalError(CGI.TheDef->getLoc(), in AsmWriterInst()
155 CGI.TheDef->getName() + "'"); in AsmWriterInst()
160 CGI.TheDef->getLoc(), in AsmWriterInst()
162 CGI.TheDef->getName() + "'"); in AsmWriterInst()
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H A DX86EVEX2VEXTablesEmitter.cpp72 OS << " { X86::" << Pair.first->TheDef->getName() in printTable()
73 << ", X86::" << Pair.second->TheDef->getName() << " },\n"; in printTable()
120 bool EVEX_W1_VEX_W0 = EVEXInst->TheDef->getValueAsBit("EVEX_W1_VEX_W0"); in operator ()()
168 Inst->TheDef->getValueAsListOfDefs("Predicates"); in run()
184 const Record *Def = Inst->TheDef; in run()
201 uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef-> in run()
207 if (!EVEXInst->TheDef->isValueUnset("EVEX2VEXOverride")) { in run()
209 EVEXInst->TheDef->getValueAsString("EVEX2VEXOverride"); in run()
223 if (EVEXInst->TheDef->getValueAsBit("hasVEX_L")) in run()
229 if (VEXInst->TheDef->getValueAsBit("checkVEXPredicate")) in run()
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H A DSubtargetFeatureInfo.h25 Record *TheDef; member
30 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {} in SubtargetFeatureInfo()
34 return "Feature_" + TheDef->getName().str(); in getEnumName()
40 return "Feature_" + TheDef->getName().str() + "Bit"; in getEnumBitName()
44 return TheDef->getValueAsBit("RecomputePerFunction"); in mustRecomputePerFunction()
H A DX86FoldTablesEmitter.cpp86 return Inst->TheDef->getName().contains(InstStr); in isExplicitAlign()
92 return Inst->TheDef->getName().contains(InstStr); in isExplicitUnalign()
118 OS << "{ X86::" << RegInst->TheDef->getName() << ","; in print()
120 OS << "X86::" << MemInst->TheDef->getName() << ","; in print()
141 bool LHSpseudo = RegInst->TheDef->getValueAsBit("isPseudo"); in operator <()
142 bool RHSpseudo = RHS.RegInst->TheDef->getValueAsBit("isPseudo"); in operator <()
146 return RegInst->TheDef->getName() < RHS.RegInst->TheDef->getName(); in operator <()
248 StringRef AltRegInstStr = I->TheDef->getValueAsString("FoldGenRegForm"); in getAltRegInst()
269 const Record *RegRec = RegInst->TheDef; in operator ()()
270 const Record *MemRec = MemInst->TheDef; in operator ()()
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H A DVarLenCodeEmitterGen.cpp115 VarLenInst::VarLenInst(const DagInit *DI, const RecordVal *TheDef) in VarLenInst() argument
116 : TheDef(TheDef), NumBits(0U) { in VarLenInst()
123 assert(TheDef && "The def record is nullptr ?"); in buildRec()
136 PrintFatalError(TheDef->getLoc(), in buildRec()
141 PrintFatalError(TheDef->getLoc(), in buildRec()
147 PrintFatalError(TheDef->getLoc(), "Unrecognized type of argument in `" + in buildRec()
155 PrintFatalError(TheDef->getLoc(), in buildRec()
160 PrintFatalError(TheDef->getLoc(), "Invalid argument types for `operand`"); in buildRec()
164 PrintFatalError(TheDef->getLoc(), "Invalid number of bits for `operand`"); in buildRec()
174 PrintFatalError(TheDef->getLoc(), in buildRec()
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H A DGICombinerEmitter.cpp142 const Record &TheDef; member in __anon8971c0cb0111::CombineRule
193 : ID(ID), TheDef(R), MatchDag(Ctx) {} in CombineRule()
201 StringRef getName() const { return TheDef.getName(); } in getName()
202 const Record &getDef() const { return TheDef; } in getDef()
248 PrintError(TheDef.getLoc(), "One or more roots are unnecessary"); in reorientToRoots()
349 DagInit *Defs = TheDef.getValueAsDag("Defs"); in parseDefs()
351 if (Defs->getOperatorAsDef(TheDef.getLoc())->getName() != "defs") { in parseDefs()
352 PrintError(TheDef.getLoc(), "Expected defs operator"); in parseDefs()
376 PrintError(TheDef.getLoc(), in parseDefs()
379 PrintError(TheDef.getLoc(), in parseDefs()
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H A DRegisterBankEmitter.cpp34 const Record &TheDef; member in __anon5db183cd0111::RegisterBank
43 RegisterBank(const Record &TheDef) in RegisterBank() argument
44 : TheDef(TheDef), RCWithLargestRegsSize(nullptr) {} in RegisterBank()
47 StringRef getName() const { return TheDef.getValueAsString("Name"); } in getName()
49 std::string getEnumeratorName() const { return (TheDef.getName() + "ID").str(); } in getEnumeratorName()
53 return (TheDef.getName() + "CoverageData").str(); in getCoverageArrayName()
57 StringRef getInstanceVarName() const { return TheDef.getName(); } in getInstanceVarName()
59 const Record &getDef() const { return TheDef; } in getDef()
H A DCodeGenSchedule.cpp120 StringRef InstName = Inst->TheDef->getName(); in apply()
123 Elts.insert(Inst->TheDef); in apply()
133 return LHS->TheDef->getName() < RHS; in apply()
136 return LHS < RHS->TheDef->getName() && in apply()
137 !RHS->TheDef->getName().startswith(LHS); in apply()
148 StringRef InstName = Inst->TheDef->getName(); in apply()
150 Elts.insert(Inst->TheDef); in apply()
605 Record *SchedDef = Inst->TheDef; in collectSchedRW()
681 findRWs(CGRW.TheDef->getValueAsListOfDefs("Writes"), CGRW.Sequence, in collectSchedRW()
732 RWVec, [Def](const CodeGenSchedRW &RW) { return RW.TheDef == Def; }); in getSchedRWIdx()
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H A DCodeGenInstruction.cpp26 CGIOperandList::CGIOperandList(Record *R) : TheDef(R) { in CGIOperandList()
205 PrintFatalError(TheDef->getLoc(), "'" + TheDef->getName() + in getOperandNamed()
237 PrintFatalError(TheDef->getLoc(), in ParseOperandName()
238 TheDef->getName() + ": Illegal operand name: '" + Op + "'"); in ParseOperandName()
248 PrintFatalError(TheDef->getLoc(), in ParseOperandName()
249 TheDef->getName() + in ParseOperandName()
260 TheDef->getLoc(), in ParseOperandName()
261 TheDef->getName() + in ParseOperandName()
274 PrintFatalError(TheDef->getLoc(), in ParseOperandName()
275 TheDef->getName() + in ParseOperandName()
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H A DVarLenCodeEmitterGen.h29 const RecordVal *TheDef; variable
40 VarLenInst() : TheDef(nullptr), NumBits(0U), HasDynamicSegment(false) {} in VarLenInst()
42 explicit VarLenInst(const DagInit *DI, const RecordVal *TheDef);
H A DInstrInfoEmitter.cpp253 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) in initOperandMapData()
266 Inst->TheDef->getName().str()); in initOperandMapData()
394 return NumberedInstructions[I]->TheDef->getName(); in emitOperandTypeMappings()
505 if (!Inst->TheDef->getValueAsBit("UseLogicalOperandMappings")) in emitLogicalOperandSizeMappings()
521 (Namespace + "::" + Inst->TheDef->getName()).str()); in emitLogicalOperandSizeMappings()
592 if (!Inst->TheDef->getValueAsBit("UseLogicalOperandMappings")) in emitLogicalOperandTypeMappings()
614 (Namespace + "::" + Inst->TheDef->getName()).str()); in emitLogicalOperandTypeMappings()
758 for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) { in emitFeatureVerifier()
761 FeatureBitsets.back().push_back(I->second.TheDef); in emitFeatureVerifier()
818 for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) { in emitFeatureVerifier()
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H A DAsmMatcherEmitter.cpp502 Record *const TheDef; member
544 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI), in MatchableInfo()
549 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef), in MatchableInfo()
552 TheDef->getValueAsBit("UseInstAsmMatchConverter")) { in MatchableInfo()
560 TheDef(RHS.TheDef), DefRec(RHS.DefRec), ResOperands(RHS.ResOperands), in MatchableInfo()
646 if (TheDef->isSubClassOf("Instruction") && in operator <()
647 TheDef->getValueAsBit("HasPositionOrder")) in operator <()
648 return TheDef->getID() < RHS.TheDef->getID(); in operator <()
812 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n"; in dump()
850 parseTwoOperandConstraint(Constraint, TheDef->getLoc()); in formTwoOperandAlias()
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H A DX86MnemonicTables.cpp46 const Record *Def = I->TheDef; in run()
75 OS << "\treturn Opcode == " << CGI->TheDef->getName() << ";\n}\n\n"; in run()
79 OS << "\tcase " << CGI->TheDef->getName() << ":\n"; in run()
H A DCompressInstEmitter.cpp273 PrintFatalError(Inst.TheDef->getLoc(), in verifyDagOpCount()
274 "Input operands for Inst '" + Inst.TheDef->getName() + in verifyDagOpCount()
278 PrintFatalError(Inst.TheDef->getLoc(), in verifyDagOpCount()
279 "Inst '" + Inst.TheDef->getName() + in verifyDagOpCount()
290 PrintFatalError(Inst.TheDef->getLoc(), in verifyDagOpCount()
291 "Inst '" + Inst.TheDef->getName() + in verifyDagOpCount()
578 return (LHS.Source.TheDef->getName() < RHS.Source.TheDef->getName()); in emitCompressInstEmitter()
580 return (LHS.Dest.TheDef->getName() < RHS.Dest.TheDef->getName()); in emitCompressInstEmitter()
667 CurOp = Source.TheDef->getName(); in emitCompressInstEmitter()
682 std::vector<Record *> RF = Dest.TheDef->getValueAsListOfDefs("Predicates"); in emitCompressInstEmitter()
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H A DCodeGenRegisters.h63 Record *const TheDef; variable
151 Record *TheDef; member
302 Record *TheDef; variable
350 Record *getDef() const { return TheDef; } in getDef()
478 if (TheDef && !TheDef->isValueUnset("BaseClassOrder")) in getBaseClassOrder()
479 return TheDef->getValueAsInt("BaseClassOrder"); in getBaseClassOrder()
488 Record *TheDef; variable
498 Record *getDef() const { return TheDef; } in getDef()
H A DAsmWriterEmitter.cpp131 << FirstInst.CGI->TheDef->getName() << ":\n"; in EmitInstructions()
134 << AWI.CGI->TheDef->getName() << ":\n"; in EmitInstructions()
146 FirstInst.CGI->TheDef->getName().str(), in EmitInstructions()
151 AWI.CGI->TheDef->getName().str(), in EmitInstructions()
189 InstrsForCase[idx] += Inst.CGI->TheDef->getName(); in FindUniqueOperandCommands()
193 InstrsForCase.push_back(std::string(Inst.CGI->TheDef->getName())); in FindUniqueOperandCommands()
423 << NumberedInstructions[i]->TheDef->getName() << "\n"; in EmitGetMnemonic()
565 AsmName = std::string(Reg.TheDef->getValueAsString("AsmName")); in emitRegisterNameString()
571 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices"); in emitRegisterNameString()
581 Reg.TheDef->getValueAsListOfStrings("AltNames"); in emitRegisterNameString()
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H A DCodeGenRegisters.cpp51 : TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) { in CodeGenSubRegIndex()
61 : TheDef(nullptr), Name(std::string(N)), Namespace(std::string(Nspace)), in CodeGenSubRegIndex()
74 if (!TheDef) in updateComponents()
77 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf"); in updateComponents()
80 PrintFatalError(TheDef->getLoc(), in updateComponents()
86 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries"); in updateComponents()
90 TheDef->getValueAsListOfDefs("CoveringSubRegIndices"); in updateComponents()
93 PrintFatalError(TheDef->getLoc(), in updateComponents()
154 : TheDef(R), EnumValue(Enum), in CodeGenRegister()
163 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices"); in buildObjectGraph()
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H A DSubtargetFeatureInfo.cpp20 errs() << getEnumName() << " " << Index << "\n" << *TheDef; in dump()
101 StringRef CondStr = SFI.TheDef->getValueAsString("CondString"); in emitComputeAvailableFeatures()
159 emitFeaturesAux(TargetName, *SFI.TheDef->getValueAsDag("AssemblerCondDag"), in emitComputeAssemblerAvailableFeatures()
H A DSubtargetEmitter.cpp868 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes")) in FindWriteResources()
869 return SchedWrite.TheDef; in FindWriteResources()
875 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) { in FindWriteResources()
876 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindWriteResources()
881 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases " in FindWriteResources()
884 AliasDef = AliasRW.TheDef; in FindWriteResources()
895 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) { in FindWriteResources()
909 SchedWrite.TheDef->getName()); in FindWriteResources()
919 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance")) in FindReadAdvance()
920 return SchedRead.TheDef; in FindReadAdvance()
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H A DCodeGenSchedule.h45 Record *TheDef; member
55 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false), in CodeGenSchedRW()
58 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { in CodeGenSchedRW()
73 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false), in CodeGenSchedRW()
79 assert((!HasVariants || TheDef) && "Variant write needs record def"); in isValid()
84 return TheDef || !Sequence.empty(); in isValid()
H A DWebAssemblyDisassemblerEmitter.cpp36 auto &Def = *CGI.TheDef; in emitWebAssemblyDisassemblerTables()
66 bool IsCanonicalExisting = CGIP.second->TheDef->getValueAsBit("IsCanonical"); in emitWebAssemblyDisassemblerTables()
H A DCodeGenInstruction.h145 Record *TheDef; // The actual record containing this OperandList. variable
231 Record *TheDef; // The actual record defining this instruction.
348 Record *TheDef; // The actual record defining this InstAlias.
H A DInstrDocsEmitter.cpp70 Record *Inst = II->TheDef; in EmitInstrDocs()
208 II->TheDef->getValueAsListOfDefs("Predicates"); in EmitInstrDocs()
H A DRegisterInfoEmitter.cpp109 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); in runEnums()
390 Record *Reg = RE.TheDef; in EmitRegMappingTables()
405 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
451 Record *Reg = RE.TheDef; in EmitRegMappingTables()
515 Record *Reg = RE.TheDef; in EmitRegMapping()
523 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMapping()
1034 OS << LS << getQualifiedName(R->TheDef); in runMCDesc()
1109 Record *Reg = RE.TheDef; in runMCDesc()
1483 if (AllocatableRegs.count(Reg.TheDef)) in runTargetDesc()
1724 ConstantSet.insert(Reg.TheDef); in runTargetDesc()
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/openbsd-src/gnu/llvm/llvm/utils/TableGen/GlobalISel/
H A DGIMatchDagPredicate.cpp33 OS << "$mi.getOpcode() == " << Instr.TheDef->getName(); in printDescription()
45 OS << Separator << Instr->TheDef->getName(); in printDescription()

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