Searched refs:RootDef (Results 1 – 2 of 2) sorted by relevance
359 ComplexRendererFns tryFoldAddLowIntoImm(MachineInstr &RootDef, unsigned Size,6440 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg()); in selectAddrModeUnscaled() local6442 MachineOperand &OffImm = RootDef->getOperand(2); in selectAddrModeUnscaled()6458 MachineOperand &Base = RootDef->getOperand(1); in selectAddrModeUnscaled()6468 AArch64InstructionSelector::tryFoldAddLowIntoImm(MachineInstr &RootDef, in tryFoldAddLowIntoImm() argument6471 if (RootDef.getOpcode() != AArch64::G_ADD_LOW) in tryFoldAddLowIntoImm()6473 MachineInstr &Adrp = *MRI.getVRegDef(RootDef.getOperand(1).getReg()); in tryFoldAddLowIntoImm()6486 auto &MF = *RootDef.getParent()->getParent(); in tryFoldAddLowIntoImm()6491 MachineIRBuilder MIRBuilder(RootDef); in tryFoldAddLowIntoImm()6513 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg()); in selectAddrModeIndexed() local[all …]
4224 if (const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg())) { in selectMUBUFScratchOffen() local4239 } else if (RootDef->getOpcode() == AMDGPU::G_FRAME_INDEX) { in selectMUBUFScratchOffen()4240 FI = RootDef->getOperand(1).getIndex(); in selectMUBUFScratchOffen()4375 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectDS1Addr1OffsetImpl() local4376 if (!RootDef) in selectDS1Addr1OffsetImpl()4391 } else if (RootDef->getOpcode() == AMDGPU::G_SUB) { in selectDS1Addr1OffsetImpl()4440 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectDSReadWrite2Impl() local4441 if (!RootDef) in selectDSReadWrite2Impl()4458 } else if (RootDef->getOpcode() == AMDGPU::G_SUB) { in selectDSReadWrite2Impl()