| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCPredicates.cpp | 18 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
20 case PPC::PRED_EQ: return PPC::PRED_NE; in InvertPredicate()
21 case PPC::PRED_NE: return PPC::PRED_EQ; in InvertPredicate()
22 case PPC::PRED_LT: return PPC::PRED_GE; in InvertPredicate()
23 case PPC::PRED_GE: return PPC::PRED_LT; in InvertPredicate()
24 case PPC::PRED_GT: return PPC::PRED_LE; in InvertPredicate()
25 case PPC::PRED_LE: return PPC::PRED_GT; in InvertPredicate()
26 case PPC::PRED_NU: return PPC::PRED_UN; in InvertPredicate()
27 case PPC::PRED_UN: return PPC::PRED_NU; in InvertPredicate()
28 case PPC::PRED_EQ_MINUS: return PPC::PRED_NE_PLUS; in InvertPredicate()
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| H A D | PPCMCTargetDesc.h | 17 #undef PPC
109 #undef PPC
182 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
183 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
184 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
185 static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
186 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
187 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
188 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
190 PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \
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| H A D | PPCInstPrinter.cpp | 63 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) && in printInst()
96 if (MI->getOpcode() == PPC::PLDpc) { in printInst()
114 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
137 if (MI->getOpcode() == PPC::RLDICR || in printInst()
138 MI->getOpcode() == PPC::RLDICR_32) { in printInst()
163 if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) && in printInst()
164 (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) { in printInst()
167 if (MI->getOpcode() == PPC::DCBTST) in printInst()
173 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE]; in printInst()
188 if (MI->getOpcode() == PPC::DCBF) { in printInst()
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| H A D | PPCAsmBackend.cpp | 35 case PPC::fixup_ppc_nofixup: in adjustFixupValue()
37 case PPC::fixup_ppc_brcond14: in adjustFixupValue()
38 case PPC::fixup_ppc_brcond14abs: in adjustFixupValue()
40 case PPC::fixup_ppc_br24: in adjustFixupValue()
41 case PPC::fixup_ppc_br24abs: in adjustFixupValue()
42 case PPC::fixup_ppc_br24_notoc: in adjustFixupValue()
44 case PPC::fixup_ppc_half16: in adjustFixupValue()
46 case PPC::fixup_ppc_half16ds: in adjustFixupValue()
47 case PPC::fixup_ppc_half16dq: in adjustFixupValue()
49 case PPC::fixup_ppc_pcrel34: in adjustFixupValue()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 140 #define NoInstr PPC::INSTRUCTION_LIST_END
143 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
144 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
145 PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \
146 PPC::RESTORE_QUADWORD \
151 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
152 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
153 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \
154 NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
159 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
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| H A D | PPCInstrInfo.cpp | 93 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP, in PPCInstrInfo()
95 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
105 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
106 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
124 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
128 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
129 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
185 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
186 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
188 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
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| H A D | PPCRegisterInfo.cpp | 99 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, in PPCRegisterInfo()
103 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; in PPCRegisterInfo()
104 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; in PPCRegisterInfo()
105 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; in PPCRegisterInfo()
106 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
107 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; in PPCRegisterInfo()
108 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
109 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
110 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
111 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; in PPCRegisterInfo()
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| H A D | PPCReturnProtectorLowering.cpp | 44 unsigned LRReg = PPC::R0; in insertReturnProtectorPrologue()
45 unsigned TOCReg = PPC::R2; in insertReturnProtectorPrologue()
46 unsigned XOR = PPC::XOR; in insertReturnProtectorPrologue()
47 unsigned LWZ = PPC::LWZ; in insertReturnProtectorPrologue()
48 unsigned MFLR = PPC::MFLR; in insertReturnProtectorPrologue()
50 LRReg = PPC::X0; in insertReturnProtectorPrologue()
51 TOCReg = PPC::X2; in insertReturnProtectorPrologue()
52 XOR = PPC::XOR8; in insertReturnProtectorPrologue()
53 LWZ = PPC::LWZ8; in insertReturnProtectorPrologue()
54 MFLR = PPC::MFLR8; in insertReturnProtectorPrologue()
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| H A D | PPCVSXSwapRemoval.cpp | 168 return (isRegInClass(Reg, &PPC::VSRCRegClass) || in isVecReg()
169 isRegInClass(Reg, &PPC::VRRCRegClass)); in isVecReg()
174 return (isRegInClass(Reg, &PPC::VSFRCRegClass) || in isScalarVecReg()
175 isRegInClass(Reg, &PPC::VSSRCRegClass)); in isScalarVecReg()
288 case PPC::XXPERMDI: { in gatherVectorInstructions()
337 case PPC::LVX: in gatherVectorInstructions()
344 case PPC::LXVD2X: in gatherVectorInstructions()
345 case PPC::LXVW4X: in gatherVectorInstructions()
351 case PPC::LXSDX: in gatherVectorInstructions()
352 case PPC::LXSSPX: in gatherVectorInstructions()
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| H A D | PPCMIPeephole.cpp | 138 assert((MF.getRegInfo().use_empty(PPC::X2) || in runOnMachineFunction()
180 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || in getKnownLeadingZeroCount()
181 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec) in getKnownLeadingZeroCount()
184 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && in getKnownLeadingZeroCount()
188 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in getKnownLeadingZeroCount()
189 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || in getKnownLeadingZeroCount()
190 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in getKnownLeadingZeroCount()
194 if (Opcode == PPC::ANDI_rec) { in getKnownLeadingZeroCount()
199 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec || in getKnownLeadingZeroCount()
200 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec || in getKnownLeadingZeroCount()
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| H A D | PPCFastISel.cpp | 144 return RC->getID() == PPC::VSFRCRegClassID; in isVSFRCRegClass()
147 return RC->getID() == PPC::VSSRCRegClassID; in isVSSRCRegClass()
159 const PPC::Predicate Pred);
162 unsigned FP64LoadOpc = PPC::LFD);
200 static std::optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) { in getComparePred()
232 return PPC::PRED_EQ; in getComparePred()
237 return PPC::PRED_GT; in getComparePred()
242 return PPC::PRED_GE; in getComparePred()
247 return PPC::PRED_LT; in getComparePred()
252 return PPC::PRED_LE; in getComparePred()
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| H A D | PPCCallingConv.cpp | 37 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_AlignArgRegs()
38 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
62 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
87 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
88 PPC::F8 in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
97 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
143 static const MCPhysReg HiRegList[] = { PPC::R3 }; in CC_PPC32_SPE_RetF64()
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| H A D | PPCRegisterInfo.h | 28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit()
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit()
30 Reg = PPC::CR0; in getCRFromCRBit()
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit()
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit()
33 Reg = PPC::CR1; in getCRFromCRBit()
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || in getCRFromCRBit()
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) in getCRFromCRBit()
36 Reg = PPC::CR2; in getCRFromCRBit()
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || in getCRFromCRBit()
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| H A D | PPCFrameLowering.cpp | 99 {PPC::F31, -8}, \ in getCalleeSavedSpillSlots()
100 {PPC::F30, -16}, \ in getCalleeSavedSpillSlots()
101 {PPC::F29, -24}, \ in getCalleeSavedSpillSlots()
102 {PPC::F28, -32}, \ in getCalleeSavedSpillSlots()
103 {PPC::F27, -40}, \ in getCalleeSavedSpillSlots()
104 {PPC::F26, -48}, \ in getCalleeSavedSpillSlots()
105 {PPC::F25, -56}, \ in getCalleeSavedSpillSlots()
106 {PPC::F24, -64}, \ in getCalleeSavedSpillSlots()
107 {PPC::F23, -72}, \ in getCalleeSavedSpillSlots()
108 {PPC::F22, -80}, \ in getCalleeSavedSpillSlots()
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| H A D | PPCTLSDynamicCall.cpp | 60 if (MI.getOpcode() != PPC::ADDItlsgdLADDR && in processBlock()
61 MI.getOpcode() != PPC::ADDItlsldLADDR && in processBlock()
62 MI.getOpcode() != PPC::ADDItlsgdLADDR32 && in processBlock()
63 MI.getOpcode() != PPC::ADDItlsldLADDR32 && in processBlock()
64 MI.getOpcode() != PPC::TLSGDAIX && in processBlock()
65 MI.getOpcode() != PPC::TLSGDAIX8 && !IsPCREL) { in processBlock()
70 if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN) in processBlock()
72 else if (MI.getOpcode() == PPC::ADJCALLSTACKUP) in processBlock()
82 Register InReg = PPC::NoRegister; in processBlock()
83 Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3; in processBlock()
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| H A D | PPCPreEmitPeephole.cpp | 62 case PPC::LBZ: in hasPCRelativeForm()
63 case PPC::LBZ8: in hasPCRelativeForm()
64 case PPC::LHA: in hasPCRelativeForm()
65 case PPC::LHA8: in hasPCRelativeForm()
66 case PPC::LHZ: in hasPCRelativeForm()
67 case PPC::LHZ8: in hasPCRelativeForm()
68 case PPC::LWZ: in hasPCRelativeForm()
69 case PPC::LWZ8: in hasPCRelativeForm()
70 case PPC::STB: in hasPCRelativeForm()
71 case PPC::STB8: in hasPCRelativeForm()
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| H A D | PPCISelDAGToDAG.cpp | 252 Align(4)) == PPC::AM_DSForm; in SelectDSForm()
260 Align(16)) == PPC::AM_DQForm; in SelectDQForm()
268 std::nullopt) == PPC::AM_DForm; in SelectDForm()
276 std::nullopt) == PPC::AM_PCRel; in SelectPCRelForm()
284 PPC::AM_PrefixDForm; in SelectPDForm()
291 std::nullopt) == PPC::AM_XForm; in SelectXForm()
299 PPC::AM_XForm; in SelectForceXForm()
467 GlobalBaseReg = PPC::R30; in INITIALIZE_PASS()
470 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR)); in INITIALIZE_PASS()
471 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in INITIALIZE_PASS()
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| H A D | PPCExpandAtomicPseudoInsts.cpp | 55 const MCInstrDesc &OR = TII->get(PPC::OR8); in PairedCopy()
56 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy()
94 case PPC::ATOMIC_SWAP_I128: in expandMI()
95 case PPC::ATOMIC_LOAD_ADD_I128: in expandMI()
96 case PPC::ATOMIC_LOAD_SUB_I128: in expandMI()
97 case PPC::ATOMIC_LOAD_XOR_I128: in expandMI()
98 case PPC::ATOMIC_LOAD_NAND_I128: in expandMI()
99 case PPC::ATOMIC_LOAD_AND_I128: in expandMI()
100 case PPC::ATOMIC_LOAD_OR_I128: in expandMI()
102 case PPC::ATOMIC_CMP_SWAP_I128: in expandMI()
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| H A D | PPCHazardRecognizers.cpp | 66 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
81 namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } } namespace
95 case PPC::Sched::IIC_IntDivW: in mustComeFirst()
96 case PPC::Sched::IIC_IntDivD: in mustComeFirst()
97 case PPC::Sched::IIC_LdStLoadUpd: in mustComeFirst()
98 case PPC::Sched::IIC_LdStLDU: in mustComeFirst()
99 case PPC::Sched::IIC_LdStLFDU: in mustComeFirst()
100 case PPC::Sched::IIC_LdStLFDUX: in mustComeFirst()
101 case PPC::Sched::IIC_LdStLHA: in mustComeFirst()
102 case PPC::Sched::IIC_LdStLHAU: in mustComeFirst()
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| H A D | PPCAsmPrinter.cpp | 354 Reg = PPC::VSX32 + (Reg - PPC::V0); in PrintAsmOperand()
356 Reg = PPC::VSX32 + (Reg - PPC::VF0); in PrintAsmOperand()
443 MII->getOpcode() == PPC::DBG_VALUE || in LowerSTACKMAP()
453 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::NOP)); in LowerSTACKMAP()
477 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LI8) in LowerPATCHPOINT()
481 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::RLDIC) in LowerPATCHPOINT()
486 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ORIS8) in LowerPATCHPOINT()
491 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ORI8) in LowerPATCHPOINT()
498 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::STD) in LowerPATCHPOINT()
499 .addReg(PPC::X2) in LowerPATCHPOINT()
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| H A D | PPCCTRLoops.cpp | 110 assert((I.getOpcode() != PPC::DecreaseCTRloop && in runOnMachineFunction()
111 I.getOpcode() != PPC::DecreaseCTR8loop) && in runOnMachineFunction()
126 return MI->definesRegister(PPC::CTR) || MI->definesRegister(PPC::CTR8); in isCTRClobber()
129 if (MI->modifiesRegister(PPC::CTR) || MI->modifiesRegister(PPC::CTR8)) in isCTRClobber()
137 if (MI->readsRegister(PPC::CTR) || MI->readsRegister(PPC::CTR8)) in isCTRClobber()
156 return MI.getOpcode() == PPC::MTCTRloop || in processLoop()
157 MI.getOpcode() == PPC::MTCTR8loop; in processLoop()
185 if (Preheader->isLiveIn(PPC::CTR) || Preheader->isLiveIn(PPC::CTR8)) in processLoop()
213 if (MI.getOpcode() == PPC::DecreaseCTRloop || in processLoop()
214 MI.getOpcode() == PPC::DecreaseCTR8loop) in processLoop()
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| H A D | PPCReduceCRLogicals.cpp | 158 OrigBROpcode == PPC::BC in splitMBB()
159 ? PPC::BCn in splitMBB()
160 : OrigBROpcode == PPC::BCn in splitMBB()
161 ? PPC::BC in splitMBB()
162 : OrigBROpcode == PPC::BCLR ? PPC::BCLRn : PPC::BCLR; in splitMBB()
225 TII->get(PPC::B)) in splitMBB()
274 if (BROp == PPC::BC || BROp == PPC::BCLR) { in computeBranchTargetAndInversion()
279 case PPC::CROR: in computeBranchTargetAndInversion()
284 case PPC::CRAND: in computeBranchTargetAndInversion()
289 case PPC::CRNAND: in computeBranchTargetAndInversion()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 99 if (RB->getID() == PPC::GPRRegBankID) { in getRegClass()
101 return &PPC::G8RCRegClass; in getRegClass()
103 return &PPC::GPRCRegClass; in getRegClass()
105 if (RB->getID() == PPC::FPRRegBankID) { in getRegClass()
107 return &PPC::F4RCRegClass; in getRegClass()
109 return &PPC::F8RCRegClass; in getRegClass()
111 if (RB->getID() == PPC::CRRegBankID) { in getRegClass()
113 return &PPC::CRBITRCRegClass; in getRegClass()
115 return &PPC::CRRCRegClass; in getRegClass()
149 case PPC::GPRRegBankID: in selectLoadStoreOp()
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| /openbsd-src/gnu/llvm/llvm/tools/llvm-exegesis/lib/PowerPC/ |
| H A D | Target.cpp | 46 return PPC::LI; in getLoadImmediateOpcode()
48 return PPC::LI8; in getLoadImmediateOpcode()
70 return TT.isArch64Bit() ? PPC::X13 : PPC::R13; in getScratchMemoryRegister()
85 setMemOp(IT, DispOpIdx, MCOperand::createReg(PPC::X1)); in fillMemoryOperands()
96 unsigned ScratchImmReg = PPC::X11; in setRegTo()
98 if (PPC::GPRCRegClass.contains(Reg)) in setRegTo()
100 if (PPC::G8RCRegClass.contains(Reg)) in setRegTo()
102 if (PPC::F4RCRegClass.contains(Reg)) in setRegTo()
104 MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)}; in setRegTo()
108 if (PPC::VRRCRegClass.contains(Reg)) in setRegTo()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 812 case PPC::DCBTx: in ProcessInstruction()
813 case PPC::DCBTT: in ProcessInstruction()
814 case PPC::DCBTSTx: in ProcessInstruction()
815 case PPC::DCBTSTT: { in ProcessInstruction()
817 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
818 PPC::DCBT : PPC::DCBTST); in ProcessInstruction()
820 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16)); in ProcessInstruction()
826 case PPC::DCBTCT: in ProcessInstruction()
827 case PPC::DCBTDS: { in ProcessInstruction()
829 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
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