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Searched refs:Opcode (Results 1 – 25 of 713) sorted by relevance

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/openbsd-src/gnu/llvm/lldb/include/lldb/Core/
H A DOpcode.h29 class Opcode {
41 Opcode() = default;
43 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
48 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
53 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
58 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
63 Opcode(uint8_t *bytes, size_t length) in Opcode() function
70 m_type = Opcode::eTypeInvalid; in Clear()
73 Opcode::Type GetType() const { return m_type; } in GetType()
77 case Opcode::eTypeInvalid:
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/openbsd-src/gnu/llvm/lldb/source/Core/
H A DOpcode.cpp24 int Opcode::Dump(Stream *s, uint32_t min_byte_width) { in Dump()
27 case Opcode::eTypeInvalid: in Dump()
30 case Opcode::eType8: in Dump()
33 case Opcode::eType16: in Dump()
36 case Opcode::eType16_2: in Dump()
37 case Opcode::eType32: in Dump()
41 case Opcode::eType64: in Dump()
45 case Opcode::eTypeBytes: in Dump()
62 lldb::ByteOrder Opcode::GetDataByteOrder() const { in GetDataByteOrder()
67 case Opcode::eTypeInvalid: in GetDataByteOrder()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h65 static BranchPredicate getBranchPredicate(unsigned Opcode);
98 unsigned Opcode) const;
102 unsigned Opcode) const;
105 MachineInstr &Inst, unsigned Opcode,
112 unsigned Opcode,
358 bool isSALU(uint16_t Opcode) const { in isSALU() argument
359 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
366 bool isVALU(uint16_t Opcode) const { in isVALU() argument
367 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
374 bool isVMEM(uint16_t Opcode) const { in isVMEM() argument
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H A DR600InstrInfo.h84 bool isALUInstr(unsigned Opcode) const;
85 bool hasInstrModifiers(unsigned Opcode) const;
86 bool isLDSInstr(unsigned Opcode) const;
87 bool isLDSRetInstr(unsigned Opcode) const;
93 bool isTransOnly(unsigned Opcode) const;
95 bool isVectorOnly(unsigned Opcode) const;
97 bool isExport(unsigned Opcode) const;
99 bool usesVertexCache(unsigned Opcode) const;
101 bool usesTextureCache(unsigned Opcode) const;
104 bool mustBeLastInClause(unsigned Opcode) const;
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/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp62 bool isLoadInst(unsigned Opcode);
76 unsigned Opcode);
96 bool BPFMISimplifyPatchable::isLoadInst(unsigned Opcode) { in isLoadInst() argument
97 return Opcode == BPF::LDD || Opcode == BPF::LDW || Opcode == BPF::LDH || in isLoadInst()
98 Opcode == BPF::LDB || Opcode == BPF::LDW32 || Opcode == BPF::LDH32 || in isLoadInst()
99 Opcode == BPF::LDB32; in isLoadInst()
118 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() local
120 if (Opcode == BPF::LDB || Opcode == BPF::LDH || Opcode == BPF::LDW || in checkADDrr()
121 Opcode == BPF::LDD || Opcode == BPF::STB || Opcode == BPF::STH || in checkADDrr()
122 Opcode == BPF::STW || Opcode == BPF::STD) in checkADDrr()
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/openbsd-src/gnu/llvm/clang/lib/AST/Interp/
H A DOpcodes.td1 //===--- Opcodes.td - Opcode defitions for the constexpr VM -----*- C++ -*-===//
95 class Opcode {
106 class AluOpcode : Opcode {
111 class IntegerOpcode : Opcode {
120 class JumpOpcode : Opcode {
138 def Ret : Opcode {
146 def RetVoid : Opcode {
152 def RetValue : Opcode {
158 def NoRet : Opcode {}
161 def Call : Opcode {
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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVMakeCompressible.cpp100 static unsigned log2LdstWidth(unsigned Opcode) { in log2LdstWidth() argument
101 switch (Opcode) { in log2LdstWidth()
119 static uint8_t compressedLDSTOffsetMask(unsigned Opcode) { in compressedLDSTOffsetMask() argument
120 return 0x1f << log2LdstWidth(Opcode); in compressedLDSTOffsetMask()
125 static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) { in compressibleSPOffset() argument
126 return log2LdstWidth(Opcode) == 2 ? isShiftedUInt<6, 2>(Offset) in compressibleSPOffset()
133 static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) { in getBaseAdjustForCompression() argument
135 return Offset & ~compressedLDSTOffsetMask(Opcode); in getBaseAdjustForCompression()
148 const unsigned Opcode = MI.getOpcode(); in isCompressibleLoad() local
150 return Opcode == RISCV::LW || (!STI.is64Bit() && Opcode == RISCV::FLW) || in isCompressibleLoad()
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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp133 static bool isXMMLoadOpcode(unsigned Opcode) { in isXMMLoadOpcode() argument
134 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
137 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
138 Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm || in isXMMLoadOpcode()
139 Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm || in isXMMLoadOpcode()
140 Opcode == X86::VMOVDQU64Z128rm || Opcode == X86::VMOVDQA64Z128rm || in isXMMLoadOpcode()
141 Opcode == X86::VMOVDQU32Z128rm || Opcode == X86::VMOVDQA32Z128rm; in isXMMLoadOpcode()
143 static bool isYMMLoadOpcode(unsigned Opcode) { in isYMMLoadOpcode() argument
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H A DX86DiscriminateMemOps.cpp75 bool IsPrefetchOpcode(unsigned Opcode) { in IsPrefetchOpcode() argument
76 return Opcode == X86::PREFETCHNTA || Opcode == X86::PREFETCHT0 || in IsPrefetchOpcode()
77 Opcode == X86::PREFETCHT1 || Opcode == X86::PREFETCHT2 || in IsPrefetchOpcode()
78 Opcode == X86::PREFETCHIT0 || Opcode == X86::PREFETCHIT1; in IsPrefetchOpcode()
116 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
134 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZTargetTransformInfo.cpp102 InstructionCost SystemZTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst() argument
117 switch (Opcode) { in getIntImmCostInst()
421 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost() argument
428 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, in getArithmeticInstrCost()
448 Opcode == Instruction::SDiv || Opcode == Instruction::SRem; in getArithmeticInstrCost()
450 Opcode == Instruction::UDiv || Opcode == Instruction::URem; in getArithmeticInstrCost()
473 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub || in getArithmeticInstrCost()
474 Opcode == Instruction::FMul || Opcode == Instruction::FDiv) in getArithmeticInstrCost()
478 if (Opcode == Instruction::FRem) in getArithmeticInstrCost()
483 if (Opcode == Instruction::Xor) { in getArithmeticInstrCost()
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H A DSystemZInstrInfo.cpp183 unsigned Opcode = getOpcodeForOffset( in expandRXYPseudo() local
186 MI.setDesc(get(Opcode)); in expandRXYPseudo()
195 unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode; in expandLOCPseudo() local
196 MI.setDesc(get(Opcode)); in expandLOCPseudo()
257 unsigned Opcode; in emitGRX32Move() local
261 Opcode = SystemZ::RISBHH; in emitGRX32Move()
263 Opcode = SystemZ::RISBHL; in emitGRX32Move()
265 Opcode = SystemZ::RISBLH; in emitGRX32Move()
271 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in emitGRX32Move()
678 unsigned Opcode = MI.getOpcode(); in isPredicable() local
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/openbsd-src/gnu/llvm/llvm/include/llvm/IR/
H A DInstruction.h192 static inline bool isUnaryOp(unsigned Opcode) {
193 return Opcode >= UnaryOpsBegin && Opcode < UnaryOpsEnd;
195 static inline bool isBinaryOp(unsigned Opcode) {
196 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd;
199 static inline bool isIntDivRem(unsigned Opcode) {
200 return Opcode == UDiv || Opcode == SDiv || Opcode == URem || Opcode == SRem;
204 static inline bool isShift(unsigned Opcode) {
205 return Opcode >= Shl && Opcode <= AShr;
219 static inline bool isBitwiseLogicOp(unsigned Opcode) {
220 return Opcode == And || Opcode == Or || Opcode == Xor;
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerInfo.cpp80 OS << Opcode << ", Tys={"; in print()
86 OS << Opcode << ", MMOs={"; in print()
265 unsigned LegalizerInfo::getOpcodeIdxForOpcode(unsigned Opcode) const { in getOpcodeIdxForOpcode()
266 assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode"); in getOpcodeIdxForOpcode()
267 return Opcode - FirstOp; in getOpcodeIdxForOpcode()
270 unsigned LegalizerInfo::getActionDefinitionsIdx(unsigned Opcode) const { in getActionDefinitionsIdx()
271 unsigned OpcodeIdx = getOpcodeIdxForOpcode(Opcode); in getActionDefinitionsIdx()
273 LLVM_DEBUG(dbgs() << ".. opcode " << Opcode << " is aliased to " << Alias in getActionDefinitionsIdx()
283 LegalizerInfo::getActionDefinitions(unsigned Opcode) const { in getActionDefinitions()
284 unsigned OpcodeIdx = getActionDefinitionsIdx(Opcode); in getActionDefinitions()
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/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegacyLegalizerInfo.h84 unsigned Opcode; member
88 InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Type(Type) {} in InstrAspect()
89 InstrAspect(unsigned Opcode, unsigned Idx, LLT Type) in InstrAspect()
90 : Opcode(Opcode), Idx(Idx), Type(Type) {} in InstrAspect()
93 return Opcode == RHS.Opcode && Idx == RHS.Idx && Type == RHS.Type;
157 const unsigned OpcodeIdx = Aspect.Opcode - FirstOp; in setAction()
179 void setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeScalarToDifferentSizeStrategy() argument
182 const unsigned OpcodeIdx = Opcode - FirstOp; in setLegalizeScalarToDifferentSizeStrategy()
190 void setLegalizeVectorElementToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeVectorElementToDifferentSizeStrategy() argument
193 const unsigned OpcodeIdx = Opcode - FirstOp; in setLegalizeVectorElementToDifferentSizeStrategy()
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/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetOpcodes.h30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode() argument
31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode() argument
37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint() argument
43 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START && in isPreISelGenericOptimizationHint()
44 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END; in isPreISelGenericOptimizationHint()
/openbsd-src/gnu/llvm/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpression.cpp123 Opcode = Data.getU8(&Offset); in extract()
125 Desc = getOpDesc(Opcode); in extract()
229 uint8_t Opcode, in prettyPrintRegisterOp() argument
237 if (Opcode == DW_OP_bregx || Opcode == DW_OP_regx || in prettyPrintRegisterOp()
238 Opcode == DW_OP_regval_type) in prettyPrintRegisterOp()
240 else if (Opcode >= DW_OP_breg0 && Opcode < DW_OP_bregx) in prettyPrintRegisterOp()
241 DwarfRegNum = Opcode - DW_OP_breg0; in prettyPrintRegisterOp()
243 DwarfRegNum = Opcode - DW_OP_reg0; in prettyPrintRegisterOp()
247 if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) || in prettyPrintRegisterOp()
248 Opcode == DW_OP_bregx) in prettyPrintRegisterOp()
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/openbsd-src/gnu/llvm/llvm/tools/llvm-readobj/
H A DARMEHABIPrinter.h99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
100 SW.startLine() << format("0x%02X ; vsp = vsp + %u\n", Opcode, in Decode_00xxxxxx()
101 ((Opcode & 0x3f) << 2) + 4); in Decode_00xxxxxx()
105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
106 SW.startLine() << format("0x%02X ; vsp = vsp - %u\n", Opcode, in Decode_01xxxxxx()
107 ((Opcode & 0x3f) << 2) + 4); in Decode_01xxxxxx()
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
125 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode); in Decode_10011101()
129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
130 SW.startLine() << format("0x%02X ; reserved (WiMMX MOVrr)\n", Opcode); in Decode_10011111()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp70 unsigned Opcode = Inst.getOpcode(); in checkCustomHazard() local
76 switch (Opcode) { in checkCustomHazard()
178 unsigned Opcode = Inst.getOpcode(); in computeWaitCnt() local
180 switch (Opcode) { in computeWaitCnt()
197 << MCII.getName(Opcode) << " will be completely " in computeWaitCnt()
200 switch (Opcode) { in computeWaitCnt()
245 unsigned Opcode = Inst->getOpcode(); in generateWaitCntInfo() local
246 const MCInstrDesc &MCID = MCII.get(Opcode); in generateWaitCntInfo()
250 if (isAlwaysGDS(Opcode) || hasModifiersSet(Inst, AMDGPU::OpName::gds)) in generateWaitCntInfo()
264 } else if (isVMEM(MCID) && !AMDGPU::getMUBUFIsBufferInv(Opcode)) { in generateWaitCntInfo()
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.h72 void EmitInt8(unsigned Opcode) { in EmitInt8() argument
73 Ops.push_back(Opcode & 0xff); in EmitInt8()
77 void EmitInt16(unsigned Opcode) { in EmitInt16() argument
78 Ops.push_back((Opcode >> 8) & 0xff); in EmitInt16()
79 Ops.push_back(Opcode & 0xff); in EmitInt16()
83 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes() argument
84 Ops.insert(Ops.end(), Opcode, Opcode + Size); in emitBytes()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonTargetTransformInfo.cpp178 InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost() argument
184 assert(Opcode == Instruction::Load || Opcode == Instruction::Store); in getMemoryOpCost()
189 if (Opcode == Instruction::Store) in getMemoryOpCost()
190 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, in getMemoryOpCost()
231 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind, in getMemoryOpCost()
236 HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, in getMaskedMemoryOpCost() argument
239 return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, in getMaskedMemoryOpCost()
252 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getGatherScatterOpCost() argument
254 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, in getGatherScatterOpCost()
259 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, in getInterleavedMemoryOpCost() argument
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/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp190 static unsigned getOppositeBranchOpc(unsigned Opcode) { in getOppositeBranchOpc() argument
191 switch (Opcode) { in getOppositeBranchOpc()
405 unsigned Opcode = 0; in storeRegToStackSlot() local
408 Opcode = CSKY::ST32W; // Optimize for 16bit in storeRegToStackSlot()
410 Opcode = CSKY::SPILL_CARRY; in storeRegToStackSlot()
413 Opcode = CSKY::FST_S; in storeRegToStackSlot()
415 Opcode = CSKY::FST_D; in storeRegToStackSlot()
417 Opcode = CSKY::f2FST_S; in storeRegToStackSlot()
419 Opcode = CSKY::f2FST_D; in storeRegToStackSlot()
428 BuildMI(MBB, I, DL, get(Opcode)) in storeRegToStackSlot()
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp232 InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst() argument
237 return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst); in getIntImmCostInst()
248 switch (Opcode) { in getIntImmCostInst()
555 InstructionCost PPCTTIImpl::vectorCostAdjustmentFactor(unsigned Opcode, in vectorCostAdjustmentFactor() argument
573 int ISD = TLI->InstructionOpcodeToISD(Opcode); in vectorCostAdjustmentFactor()
587 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost() argument
591 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode"); in getArithmeticInstrCost()
593 InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Ty, nullptr); in getArithmeticInstrCost()
599 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, in getArithmeticInstrCost()
604 Opcode, Ty, CostKind, Op1Info, Op2Info); in getArithmeticInstrCost()
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp178 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
184 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
221 unsigned Opcode = MI.getOpcode(); in getMemoryOpOffset() local
222 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
226 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
227 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
228 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
229 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
233 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
234 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCPredicates.h70 Predicate InvertPredicate(Predicate Opcode);
74 Predicate getSwappedPredicate(Predicate Opcode);
77 inline unsigned getPredicateCondition(Predicate Opcode) { in getPredicateCondition() argument
78 return (unsigned)(Opcode & ~BR_HINT_MASK); in getPredicateCondition()
82 inline unsigned getPredicateHint(Predicate Opcode) { in getPredicateHint() argument
83 return (unsigned)(Opcode & BR_HINT_MASK); in getPredicateHint()
/openbsd-src/gnu/llvm/llvm/include/llvm/MC/
H A DMCInstrInfo.h63 const MCInstrDesc &get(unsigned Opcode) const { in get() argument
64 assert(Opcode < NumOpcodes && "Invalid opcode!"); in get()
66 return *(LastDesc - Opcode); in get()
70 StringRef getName(unsigned Opcode) const { in getName() argument
71 assert(Opcode < NumOpcodes && "Invalid opcode!"); in getName()
72 return StringRef(&InstrNameData[InstrNameIndices[Opcode]]); in getName()

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