Searched refs:MSR_MISC_ENABLE (Results 1 – 6 of 6) sorted by relevance
279 rdmsr_safe(MSR_MISC_ENABLE, &msr) == 0 && in x86_print_cacheinfo()
1241 rdmsr_safe(MSR_MISC_ENABLE, &msr) == 0 && in cpu_fix_msrs() 1244 wrmsr(MSR_MISC_ENABLE, msr); in cpu_fix_msrs()
2313 msr_misc_enable = rdmsr(MSR_MISC_ENABLE); in vcpu_reset_regs_vmx() 2331 msr_store[VCPU_HOST_REGS_MISC_ENABLE].vms_index = MSR_MISC_ENABLE; in vcpu_reset_regs_vmx() 2345 msr_store[VCPU_REGS_MISC_ENABLE].vms_index = MSR_MISC_ENABLE; in vcpu_reset_regs_vmx() 2348 * Initialize MSR_MISC_ENABLE as it can't be read and populated from vmd in vcpu_reset_regs_vmx() 2454 vmx_setmsrbr(vcpu, MSR_MISC_ENABLE); in vcpu_reset_regs_vmx() 5472 * Handler for writes to the MSR_MISC_ENABLE (0x1a0) MSR on Intel CPUs. We5542 case MSR_MISC_ENABLE: in vmx_handle_cr() 7805 case MSR_MISC_ENABLE: return "Misc Enable"; in vmx_vcpu_dump_regs() 8136 case MSR_MISC_ENABLE: vmm_decode_misc_enable_value(val); break;
405 #define MSR_MISC_ENABLE 0x1a0 macro
560 #define MSR_MISC_ENABLE 0x1a0 macro 562 * MSR_MISC_ENABLE (0x1a0)
1072 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) in cyrix3_setperf_setup() 1470 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) in intel686_setperf_setup()