| /openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/ |
| H A D | SparcFrameLowering.cpp | 45 unsigned ADDri) const { in emitSPAdjustment()
52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
115 SAVEri = SP::ADDri; in emitPrologue()
179 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased) in emitPrologue()
192 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6) in emitPrologue()
208 emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri); in eliminateCallFramePseudoInstr()
233 emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri); in emitEpilogue()
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| H A D | SparcFrameLowering.h | 62 int NumBytes, unsigned ADDrr, unsigned ADDri) const;
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| H A D | DelaySlotFiller.cpp | 507 case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break; in tryCombineRestoreWithPrevInst()
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| H A D | SparcInstrAliases.td | 429 def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
432 def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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| H A D | SparcInstrInfo.td | 1799 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1808 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1809 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1811 (ADDri $r, tblockaddress:$in)>;
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | README.txt | 35 %reg1037 = ADDri %reg1039, 1
43 Note ADDri is not a two-address instruction. However, its result %reg1037 is an
45 PHI node. We should treat it as a two-address code and make sure the ADDri is
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMMCInstLower.cpp | 139 case ARM::ADDri: in LowerARMMachineInstrToMCInst()
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| H A D | ARMInstructionSelector.cpp | 107 unsigned ADDri; member
320 STORE_OPCODE(ADDri, ADDri); in OpcodeCache()
1073 I.setDesc(TII.get(Opcodes.ADDri)); in select()
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| H A D | ARMBaseInstrInfo.cpp | 229 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
260 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
2436 {ARM::ADDSri, ARM::ADDri},
2511 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
2656 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex()
2914 OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) && in isRedundantFlagInstr()
2966 case ARM::ADDri: in isOptimizeCompareCandidate()
3384 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri; in FoldImmediate()
3387 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri; in FoldImmediate()
4959 unsigned AddOpc = (LoadImmOpc == ARM::MRC) ? ARM::ADDri : ARM::t2ADDri; in expandLoadStackGuardBase()
[all …]
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| H A D | ARMAsmPrinter.cpp | 1243 case ARM::ADDri: in EmitUnwindingInstruction()
2016 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in emitInstruction()
2043 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in emitInstruction()
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| H A D | ARMBaseRegisterInfo.cpp | 669 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : in materializeFrameBaseRegister()
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| H A D | ARMScheduleM55.td | 55 // NOPs, ITs, Brs, ADDri/SUBri, UXTB/H, SXTB/H and MOVri's. NOPs and IT's are
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| H A D | ARMLoadStoreOptimizer.cpp | 709 : isThumb1 ? ARM::tADDi8 : ARM::ADDri; in CreateLoadStoreMulti()
1202 case ARM::ADDri: Scale = 1; CheckCPSRDef = true; break; in isIncrementOrDecrement()
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| H A D | ARMFrameLowering.cpp | 1915 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; in emitAlignedDPRCS2Restores()
2109 if (MI.getOpcode() == ARM::ADDri) { in estimateRSStackSizeLimit()
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| H A D | ARMFastISel.cpp | 656 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in fastMaterializeAlloca()
834 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress()
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| H A D | ARMInstrInfo.td | 6347 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6349 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
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| H A D | ARMISelDAGToDAG.cpp | 3766 ARM::t2ADDri : ARM::ADDri); in Select()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 731 const MCInstrDesc &ADDri = in processInstructionForSlowLEA() local
734 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), ADDri, DstR) in processInstructionForSlowLEA()
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| H A D | X86FrameLowering.cpp | 3686 unsigned ADDri = getADDriOpcode(false, EndOffset); in restoreWin32EHStackPointers() local
3687 BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr) in restoreWin32EHStackPointers()
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| /openbsd-src/gnu/llvm/llvm/docs/ |
| H A D | WritingAnLLVMBackend.rst | 729 LLVM target could model this with two instructions named ``ADDri`` and
819 ``XORri``, ``ADDrr``, and ``ADDri``.
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 8788 case ARM::ADDri: { in processInstruction()
|